Monolithic ic with complementary transistors and plural buried layers

Claim 2

A semiconductor device comprising within a common monocrystal one type and complementary type transistors, said monocrystal comprising a substrate portion predominantly of one conductivity type and on the surface thereof a single deposited epitaxial layer of the opposite conductivity type united in monocrystalline relation therewith and containing walls of said one conductivity type extending from the said deposited layer surface to the substrate defining a plurality of islands of the opposite conductivity type, at least one island containing a first one type transistor and at least another island containing a second complementary type transistor, said one type transistor comprising first emitter, base and collector regions alternating in conductivity type, said first base region surrounding the first emitter region and both extending to the said deposited layer surface, said first collector region including the island area surrounding the first base region and also extending to the said deposited layer surface, said complementary transistor comprising second emitter, base and collector regions alternating in conductivity type, said complementary second emitter being a surface region of the island, said second base region including the island area surrounding the second emitter and extending to the said deposited layer surface, said second collector region comprising a first buried layer of said one conductivity type extending into said opposite type deposited layer substantially from the substrate and up to but spaced from the surface of said deposited layer and said second emitter and underlying the latter leaving between said second emitter and the first buried layer a part of the island area constituting a part of the second base region and contact regions for the first buried layer and of one conductivity type and extending from the said deposited layer surface to the first buried layer, said device further including a second buried layer of opposite type conductivity extending underneath the first buried layer and connected to island areas of opposite conductivity type extending to the layer surface, the first buried layer being totally separated from substrate parts of one conductivity type and from said walls of one conductivity type defining the islands by the second buried layer and the island areas connected thereto of opposite conductivity type, the first emitter and the first base regions of the one-type transistor and the second emitter and the collector contact regions of the complementary transistor having doping impurity concentrations that decrease away from the said deposited layer surface, and means for making connections to the emitter, base and collector regions of both transistors.

Claim 3

A device as set forth in claim 1 wherein the first collector region of said one type transistor comprises a third buried layer of opposite conductivity type extending from the substrate toward but spaced from the base region and underlying the latter.

Claim 4

A device as set forth in claim 2 wherein the first, second and third buried layers have a doping impurity concentration in the opposite-type said deposited layer that decreases in the direction from the substrate toward the deposited layer surface.

Claim 5

A device as set forth in claim 1 wherein underneath the first buried layer the second buried layer lies throughout its thickness in the substrate.

Claim 6

A device as set forth in claim 1 wherein the second collector contact regions completely surround the second emitter.

Claim 7

A device as set forth in claim 1 wherein the first buried layer lies throughout its thickness in the deposited epitaxial layer.

Claim 8

A semiconductor device comprising within a common monocrystal one type NPN and complementary type PNP transistors, said monocrystal comprising a substrate portion predominantly of one conductivity type and on the entire surface thereof a single epitaxial layer of the opposite conductivity type united in monocrystalline relation therewith and containing walls of said one conductivity type extending from the epitaxial layer surface to the substrate defining a plurality of islands of the opposite conductivity type, at least one island containing an NPN type transistor and at least another island containing a complementary PNP type transistor, said one type transistor comprising first emitter, base and collector regions alternating in conductivity type, said first base region surrounding the first emitter region and both extending to the layer surface, said first collector region including the island area surrounding the first base region and also extending to the layer surface, said complementary transistor comprising second emitter, base and collector regions alternating in conductivity type, said complementary second emitter being a surface region of the island, said second base region including the unaltered island area surrounding the second emitter and extending to the layer surface, said second collector region comprising a first buried layer of said one conductivity type extending into the opposite type epitaxial layer substantially from the substrate and up to but spaced from the surface of said epitaxial layer and said second emitter and underlying the latter leaving between said second emitter and the first buried layer a part of the island area constituting a part of the second base region and contact regions for the first buried layer spaced from the walls of one conductivity type and extending from the epitaxial layer surface to the first buried layer, said device further including a second buried layer of opposite type conductivity extending underneath the first buried layer and connected to island areas of opposite conductivity type extending to the layer surface, the first buried layer being completely separated from substrate portions of one type conductivity and the said one type walls by the second buried layer and opposite-type connected island regions, the first emitter and the first base regions of the one-type transistor and the second emitter and collector contact regions of the complementary transistor having doping impurity concentrations that decrease away from the layer surface, said first buried layer of the second collector of the complementary transistor having a doping impurity concentration in the opposite type epitaxial layer that decreases in a direction from the vicinity of the substrate-layer junction toward the layer surface, and said second buried layer having a substantially maximum doping impurity concentration substantially at the substrate-layer junction, and means for making connections to the emitter, base and collector regions of both transistors.

Claim 9

A semiconductor device comprising within a common monocrystal one type NPN and complementary type PNP transistors, said monocrystal comprising a substrate portion predominantly of one conductivity type and on the entire surface thereof a single epitaxial layer of the opposite conductivity type united in monocrystalline relation therewith and containing walls of said one conductivity type extending from the epitaxial layer surface to the substrate defining a plurality of islands of the opposite conductivity type, at least one island containing an NPN type transistor and at least another island containing a complementary PNP type transistor, said one type transistor comprising first emitter, base and collector regions alternating in conductivity type, said first base region surrounding the first emitter region and both extending to the layer surface, said first collector region including the island area surrounding the first base region and also extending to the layer surface, said complementary transistor comprising second emitter, base and collector regions alternating in conductivity type, said complementary second emitter being a surface region of the island, said second base region including the unaltered island area surrounding the second emitter and extending to the layer surface, said second collector region comprising a first buried layer of said one conductivity type extending into the opposite type epitaxial layer substantially from the substrate and up to but spaced from the surface of said epitaxial layer and said second emitter and underlying the latter leaving between said second emitter and the first buried layer a part of the island area constituting a part of the second base region and contact regions for the first buried layer spaced from the walls of one conductivity type and extending from the epitaxial layer surface to the first buried layer, said device further including a second buried layer of opposite type conductivity extending underneath the first buried layer and connected to island areas of opposite conductivity type extending to the layer surface, the first buried layer being completely separated from substrate portions of one type conductivity and the said one type walls by the second buried layer and opposite-type connected island regions, the first emitter and the first base regions of the one-type transistor and the second emitter and collector contact regions of the complementary transistor having doping impurity concentrations that decrease away from the layer surface, said first buried layer of the second collector of the complementary transistor having a doping impurity concentration in the opposite type epitaxial layer that decreases in a direction from the vicinity of the substrate-layer junction toward the layer surface, and said second buried layer having a substantially maximum doping impurity concentration substantially at the substrate-layer junction, and means for making connections to the emitter, base and collector regions of both transistors.

Claim 10

A device as set forth in claim 7 wherein the first base and the second emitter have the same resistivity and impurity concentration profile, and the second collector contact region portions and the island defining wall portions adjacent the surface have the same resistivity and impurity concentration profile.

Claim 11

A device as set forth in claim 7 wherein said island defining isolation walls have a doping impurity concentration that decreases from both the layer surface and the substrate-layer junction toward the interior of the epitaxial layer.

Claim 12

A device as set forth in claim 7 wherein the first collector region of the one-type transistor and the second base region including the island area of the complementary transistor contain substantial areas where the doping impurity concentrations are substantially uniform.

Claim 13

A semiconductor structure comprising: a unitary body of semiconductor material having a substrate of a first conductivity type; a layer of semiconductor material of the opposite conductivity type disposed on said substrAte and having an exposed substantially planar surface; means extending from said surface to said substrate for providing first and second electrically isolated semiconductor regions within said layer; a third semiconductor region of said first conductivity type disposed within said first region and forming a PN junction that extends to said surface; a fourth semiconductor region of said opposite conductivity type disposed within said third region and forming a PN junction that extends to said surface whereby said first, third, and fourth regions comprise a first vertical transistor wherein said third region serves as the base region and said first and fourth regions serve as the collector and emitter regions; a layer of semiconductor material of said first conductivity type buried within said second region remote from said surface and remote from said substrate; a fifth semiconductor region of said first conductivity type formed within said second region and extending from said surface to said buried layer and joining therewith to form a composite region, said fifth region having a closed geometrical shape so that said composite region encloses a portion of said second region, said enclosed portion of said second region forming a PN junction with said composite region which extends to said surface; and a sixth semiconductor region of said first conductivity type located within said enclosed portion of said second region and forming a PN junction therewith which extends to said surface, so that said enclosed portion of said second region, said composite region and said sixth region form a structure operable as a second vertical transistor having a polarity opposite to that of said first transistor wherein said enclosed portion of said second region serves as the base region, and said composite region and said sixth region serve as the emitter and collector regions.

Claim 14

A semiconductor structure comprising: a unitary body of semiconductor material having a substrate of a first conductivity type; a layer of semiconductor material of the opposite conductivity type disposed on said substrAte and having an exposed substantially planar surface; means extending from said surface to said substrate for providing first and second electrically isolated semiconductor regions within said layer; a third semiconductor region of said first conductivity type disposed within said first region and forming a PN junction that extends to said surface; a fourth semiconductor region of said opposite conductivity type disposed within said third region and forming a PN junction that extends to said surface whereby said first, third, and fourth regions comprise a first vertical transistor wherein said third region serves as the base region and said first and fourth regions serve as the collector and emitter regions; a layer of semiconductor material of said first conductivity type buried within said second region remote from said surface and remote from said substrate; a fifth semiconductor region of said first conductivity type formed within said second region and extending from said surface to said buried layer and joining therewith to form a composite region, said fifth region having a closed geometrical shape so that said composite region encloses a portion of said second region, said enclosed portion of said second region forming a PN junction with said composite region which extends to said surface; and a sixth semiconductor region of said first conductivity type located within said enclosed portion of said second region and forming a PN junction therewith which extends to said surface, so that said enclosed portion of said second region, said composite region and said sixth region form a structure operable as a second vertical transistor having a polarity opposite to that of said first transistor wherein said enclosed portion of said second region serves as the base region, and said composite region and said sixth region serve as the emitter and collector regions.

Claim 15

The semiconductor structure of claim 11 further comprising a highly conductive semiconductive layer of said opposite conductivity type located within said second region and extending from said substrate to said buried layer.

Claim 16

The semiconductor structure of claim 12 wherein said means for electrically isolating said first and second regions comprises a semiconductor region of said first conductivity type.

Claim 17

A semiconductor structure comprising: a unitary body of semiconductor material having a substrate of a first conductivity type; a layer of semiconductor material of the opposite conductivity type disposed on said substrate and having an exposed substantially planar surface; means extending from said surface to said substrate for providing first and second electrically isolated semiconductor regions within said layer; a third semiconductor region of said first conductivity type disposed within said first region and forming a PN junction that extends to said surface; a fourth semiconductor region of said opposite conductivity type disposed within said third region and forming a PN junction that extends to said surface whereby said first, third, and fourth regions comprise a first vertical transistor; a layer of semiconductor material of said first conductivity type buried within said second region remote from said surface and remote from said substrate; a fifth semiconductor region of said first conductivity type formed within said second region and extending from said surface to said buried layer and joining therewith to form a composite region, said fifth region having a closed geometrical shape so tat said composite region encloses a portion of said second region, said enclosed portion of said second region forming a PN junction with said composite region which extends to said surface; and a sixth semiconductor region of said first conductivity type located within said enclosed portion of said second region and forming a PN junction therewith which extends to said surface, so that said enclosed portion of said seconD region, said composite region and said sixth region form a structure operable as a second vertical transistor having a polarity opposite to that of said first transistor.

Claim 18

A semiconductor structure comprising: a unitary body of semiconductor material having a substrate of a first conductivity type; a layer of semiconductor material of the opposite conductivity type disposed on said substrate and having an exposed substantially planar surface; means extending from said surface to said substrate for providing first and second electrically isolated semiconductor regions within said layer; a third semiconductor region of said first conductivity type disposed within said first region and forming a PN junction that extends to said surface; a fourth semiconductor region of said opposite conductivity type disposed within said third region and forming a PN junction that extends to said surface whereby said first, third, and fourth regions comprise a first vertical transistor; a layer of semiconductor material of said first conductivity type buried within said second region remote from said surface and remote from said substrate; a fifth semiconductor region of said first conductivity type formed within said second region and extending from said surface to said buried layer and joining therewith to form a composite region, said fifth region having a closed geometrical shape so tat said composite region encloses a portion of said second region, said enclosed portion of said second region forming a PN junction with said composite region which extends to said surface; and a sixth semiconductor region of said first conductivity type located within said enclosed portion of said second region and forming a PN junction therewith which extends to said surface, so that said enclosed portion of said seconD region, said composite region and said sixth region form a structure operable as a second vertical transistor having a polarity opposite to that of said first transistor.