Patent US5981384A successfully refreshed from Google Patents.
US5981384A
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Method of intermetal dielectric planarization by metal features layout modification
Assignee: Micron Technology Inc
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Filing: 1995-08-14
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Granted: 1999-11-09
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Expires: 2015-08-14
Abstract
Abstract A technique is disclosed for general IC structures to modify the layout of electrically unisolated metal lines before patterning same so that the spacing between the metal lines is substantially standardized prior to performing deposition of an intermetal dielectric layer. Upon such standardization of metal line spacing, the intermetal dielectric will be planarized in a single process step of deposition. Circuit layout design modifications can be made by adding electrically isolated dummy metal line features in areas of the layout having open spaces between parallel metal lines, and adding metal line spacers to existing metal lines to reduce the spacing between the metal lines and dummy metal features. As the nonstandard spacing between metal lines becomes standardized, an internetal dielectric deposition results in a planarized surface of the intermetal dielectric. Consequently, many conventional process steps for planarizing the intermetal dielectric can be skipped or simplified.
Inventors
- 👤 Werner Juengling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:53
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/01; H10W20/071; H10W20/092; Y; Y10; Y10S; Y10S438/00; Y10S438/926
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
271 words
A method of fabricating an IC structure comprising: patterning a plurality of electrically unisolated metal lines on a substrate, said plurality of metal lines including at least three substantially parallel metal lines, each said electrically unisolated metal line: having a substantially equal height T MET and being parallel one with another; and being separated from the nearest of the other electrically unisolated metal lines; patterning n electrically isolated metal lines each: having a width W met ; and being situated in the separation between the electrically unisolated metal line and the nearest of the other electrically unisolated metal lines; wherein there is a separation S met between: each electrically unisolated metal line and the nearest of one of: another electrically unisolated metal line; or one of said electrically isolated metal lines; each electrically isolated metal line and the nearest of one of: another electrically isolated metal line; or one of said electrically unisolated metal lines; depositing a dielectric layer having a thickness of T idl over: said plurality of electrically unisolated metal lines; and said n electrically isolated metal lines, wherein: S met is not greater than (1.4(n+1)T idl )+(n)W met ) or twice T idl ; n is a maximized whole number not greater than (S met -1.4T idl )/(1.4T idl +W met ); one of said plurality of electrically isolated or unisolated metal lines is diagonally spaced from the nearest portion of another one of said plurality of electrically isolated or unisolated metal lines by a distance that is equal to √2*S met ; and said thickness of T idl has a value of at least (√2*S met )÷2.
Claim 2
Independent Claim
271 words
A method of fabricating an IC structure comprising: patterning a plurality of electrically unisolated metal lines on a substrate, said plurality of metal lines including at least three substantially parallel metal lines, each said electrically unisolated metal line: having a substantially equal height T MET and being parallel one with another; and being separated from the nearest of the other electrically unisolated metal lines; patterning n electrically isolated metal lines each: having a width W met ; and being situated in the separation between the electrically unisolated metal line and the nearest of the other electrically unisolated metal lines; wherein there is a separation S met between: each electrically unisolated metal line and the nearest of one of: another electrically unisolated metal line; or one of said electrically isolated metal lines; each electrically isolated metal line and the nearest of one of: another electrically isolated metal line; or one of said electrically unisolated metal lines; depositing a dielectric layer having a thickness of T idl over: said plurality of electrically unisolated metal lines; and said n electrically isolated metal lines, wherein: S met is not greater than (1.4(n+1)T idl )+(n)W met ) or twice T idl ; n is a maximized whole number not greater than (S met -1.4T idl )/(1.4T idl +W met ); one of said plurality of electrically isolated or unisolated metal lines is diagonally spaced from the nearest portion of another one of said plurality of electrically isolated or unisolated metal lines by a distance that is equal to √2*S met ; and said thickness of T idl has a value of at least (√2*S met )÷2.
Claim 3
Dependent Claim
44 words
The method for fabricating the IC structure as defined in claim 1, wherein the maximum spacing between nearest diagonally spaced points on said electrically isolated or electrically unisolated metal lines is less than or equal to about twice the thickness of the dielectric layer.
Claim 4
Dependent Claim
43 words
The method for fabricating the IC structure as defined in claim 1, wherein the minimum width of said electrically isolated or electrically unisolated metal lines and the minimum spacing between the closest parallel electrically isolated or electrically unisolated metal lines are about equal.
Claim 5
Dependent Claim
21 words
The method for fabricating the IC structure as defined in claim 1, wherein said dielectric layer is planarized upon said depositing.
Claim 6
Dependent Claim
29 words
The method for fabricating the IC structure as defined in claim 1, wherein at least one electrically isolated metal line is situated between two nearest electrically unisolated metal lines.
Claim 7
Dependent Claim
37 words
The method for fabricating the IC structure as defined in claim 1, wherein each of the electrically unisolated metal lines has a length and a width, and wherein the width of the electrically unisolated metal lines varies.
Claim 8
Dependent Claim
46 words
The method for fabricating the IC structure as defined in claim 1, further comprising a guard ring circumscribing said electrically isolated or electrically unisolated metal lines, said guard ring having said separation S met to the nearest electrically isolated or electrically unisolated metal line parallel thereto.
Claim 9
Dependent Claim
100 words
The method of fabricating the IC structure as defined in claim 1, further comprising: applying a layer of photoresist over said dielectric layer; exposing said layer of photoresist in an area positioned over at least one metal line of said electrically unisolated metal lines; developing said layer of photoresist to open at least one via positioned over said at least one metal line of said electrically unisolated metal lines; and depositing a second metal line into said at least one via so as to make underlying contact with said at least one metal line of said electrically unisolated metal lines.
Claim 10
Dependent Claim
66 words
The method for fabricating the IC structure as defined in claim 8, further comprising repeating at least once: depositing a dielectric layer; applying, exposing and developing a layer of photoresist to create at least one via; and depositing at least a second metal line into said at least one via to make underlying contact with at least one metal line of said electrically unisolated metal lines.
Claim 11
Independent Claim
292 words
A method of fabricating an IC structure comprising: patterning a plurality of electrically unisolated metal lines on a substrate each: having a height T MET and being parallel one with another; and being separated from the nearest of the other electrically unisolated metal lines; patterning n electrically isolated metal lines each: having a width W met ; and being situated in the separation between each electrically unisolated metal line and the nearest of the other electrically unisolated metal lines; wherein there is a separation S met between: each electrically unisolated metal line and the nearest of one of: another electrically unisolated metal line; or one of said electrically isolated metal lines; each electrically isolated metal line and the nearest of one of: another electrically isolated metal line; or one of said electrically unisolated metal lines; depositing a dielectric layer having a thickness of T idl over the electrically isolated and unisolated metal lines, wherein: S met is not greater than (1.4(n+1)T idl )+(n)W met ) or twice T idl ; n is a maximized whole number not greater than (S met -1.4T idl )/(1.4T idl +W met ); when n is equal to zero, then one electrically unisolated metal line of said plurality of electrically unisolated metal lines has a first width and the nearest of said plurality of electrically unisolated metal lines has a second width; said first width is different from said second width; one of said plurality of electrically isolated or unisolated metal lines is diagonally spaced from the nearest portion of another one of said plurality of electrically isolated or unisolated metal lines by a distance that is equal to √2*S met ; and said thickness of T idl has a value of at least (√2*S met )÷2.
Claim 12
Independent Claim
292 words
A method of fabricating an IC structure comprising: patterning a plurality of electrically unisolated metal lines on a substrate each: having a height T MET and being parallel one with another; and being separated from the nearest of the other electrically unisolated metal lines; patterning n electrically isolated metal lines each: having a width W met ; and being situated in the separation between each electrically unisolated metal line and the nearest of the other electrically unisolated metal lines; wherein there is a separation S met between: each electrically unisolated metal line and the nearest of one of: another electrically unisolated metal line; or one of said electrically isolated metal lines; each electrically isolated metal line and the nearest of one of: another electrically isolated metal line; or one of said electrically unisolated metal lines; depositing a dielectric layer having a thickness of T idl over the electrically isolated and unisolated metal lines, wherein: S met is not greater than (1.4(n+1)T idl )+(n)W met ) or twice T idl ; n is a maximized whole number not greater than (S met -1.4T idl )/(1.4T idl +W met ); when n is equal to zero, then one electrically unisolated metal line of said plurality of electrically unisolated metal lines has a first width and the nearest of said plurality of electrically unisolated metal lines has a second width; said first width is different from said second width; one of said plurality of electrically isolated or unisolated metal lines is diagonally spaced from the nearest portion of another one of said plurality of electrically isolated or unisolated metal lines by a distance that is equal to √2*S met ; and said thickness of T idl has a value of at least (√2*S met )÷2.
Claim 13
Dependent Claim
44 words
The method for fabricating the IC structure as defined in claim 10, wherein the maximum spacing between nearest diagonally spaced points on said electrically isolated or electrically unisolated metal lines is less than or equal to about twice the thickness of the dielectric layer.
Claim 14
Dependent Claim
43 words
The method for fabricating the IC structure as defined in claim 10, wherein the minimum width of said electrically isolated or electrically unisolated metal lines and the minimum spacing between the closest parallel electrically isolated or electrically unisolated metal lines are about equal.
Claim 15
Dependent Claim
21 words
The method for fabricating the IC structure as defined in claim 10, wherein said dielectric layer is planarized upon said depositing.
Claim 16
Dependent Claim
29 words
The method for fabricating the IC structure as defined in claim 10, wherein at least one electrically isolated metal line is situated between two nearest electrically unisolated metal lines.
Claim 17
Dependent Claim
45 words
The method for fabricating the IC structure as defined in claim 10, wherein each of the electrically unisolated metal lines of said plurality of electrically unisolated metal lines has a length and a width, and wherein the width of the electrically unisolated metal lines varies.
Claim 18
Dependent Claim
46 words
The method for fabricating the IC structure as defined in claim 10, further comprising a guard ring circumscribing said electrically isolated or electrically unisolated metal lines, said guard ring having said separation S met to the nearest electrically isolated or electrically unisolated metal line parallel thereto.
Claim 19
Dependent Claim
100 words
The method of fabricating the IC structure as defined in claim 10, further comprising: applying a layer of photoresist over said dielectric layer; exposing said layer of photoresist in an area positioned over at least one metal line of said electrically unisolated metal lines; developing said layer of photoresist to open at least one via positioned over said at least one metal line of said electrically unisolated metal lines; and depositing a second metal line into said at least one via so as to make underlying contact with said at least one metal line of said electrically unisolated metal lines.
Claim 20
Dependent Claim
66 words
The method for fabricating the IC structure as defined in claim 17, further comprising repeating at least once: depositing a dielectric layer; applying, exposing and developing a layer of photoresist to create at least one via; and depositing at least a second metal line into said at least one via to make underlying contact with at least one metal line of said electrically unisolated metal lines.
Claim 21
Independent Claim
167 words
A method of fabricating an IC structure comprising: providing a substrate; patterning on the substrate metal lines that are electrically unisolated and metal features that are electrically isolated; and forming a planar dielectric layer having a thickness of T idl over said metal lines and said metal features, wherein: the height of the metal lines and metal features are the same; there is a space between respective adjacent metal lines, and within at least one of said spaces there are n of said metal features each having a width substantially equal to W met and being separated from adjacent metal features and from any adjacent metal lines by a separation distance that is less than or equal to 2*T idl where T idl is a constant and n is a positive integer that satisfies the expression: n*W met ≦W sp ≦(( (n+1)*1.4*T idl )+n*W met ), wherein W sp is the width of said at least one of said spaces that has therein said n metal features.
Claim 22
Independent Claim
167 words
A method of fabricating an IC structure comprising: providing a substrate; patterning on the substrate metal lines that are electrically unisolated and metal features that are electrically isolated; and forming a planar dielectric layer having a thickness of T idl over said metal lines and said metal features, wherein: the height of the metal lines and metal features are the same; there is a space between respective adjacent metal lines, and within at least one of said spaces there are n of said metal features each having a width substantially equal to W met and being separated from adjacent metal features and from any adjacent metal lines by a separation distance that is less than or equal to 2*T idl where T idl is a constant and n is a positive integer that satisfies the expression: n*W met ≦W sp ≦(( (n+1)*1.4*T idl )+n*W met ), wherein W sp is the width of said at least one of said spaces that has therein said n metal features.
Claim 23
Dependent Claim
52 words
The method for fabricating the IC structure as defined in claim 19, wherein: when n is equal to zero, then one metal line of said metal lines has a first width and the nearest of said metal lines has a second width; and said first width is different from said second width.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-08 | 2003-05-10 | 2003-11-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-08 | 2007-05-10 | 2007-11-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-08 | 2011-05-10 | 2011-11-09 | $7700.00 | Window Closed / Lapsed |