US5453406A
Expired / Lapsed
US
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Aspect ratio independent coating for semiconductor planarization using SOG
Assignee: Industrial Technology Research Institute
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Filing: 1994-06-13
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Granted: 1995-09-26
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Expires: 2014-06-13
Abstract
Abstract A new method for forming a planarized dielectric layer on a patterned conducting layer was accomplished. The method involves forming a insulating layer over a semiconductor substrate having semiconductor devices formed therein. A metal conducting layer is deposited and then patterned by anisotropically etching. The patterned conducting layer is used to make the electrical connections to the device contact. A barrier insulator is deposited on the patterned conducting layer to keep the conducting layer from coming into contact with the spin-on-glass and eroding. A planar dielectric layer is formed over the patterned conducting layer by coating a first spin-on-glass layer at a constant and low speed and then baking and then a second spin-on-glass layer is coated on the first spin-on-glass layer at a constant and high speed and then cured forming an improved planarized dielectric layer.
Inventors
- 👤 Lai-Juh Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:10
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/66; H10P14/662; H10P14/6342; H10P14/69215
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
188 words
A method for forming a planarized dielectric layer over a substrate having a patterned conducting layer comprising the steps of: providing a semiconductor substrate having semiconductor devices formed in and on said substrate and having a patterned conducting layer formed thereon; depositing an insulating layer on said semiconductor devices and said patterned conducting layer; coating said insulating layer with a first spin-on-glass layer dispensed at a first and constant spin speed of between about 600 to 800 revolutions per minute (rpm) and thereby partially filling recesses formed by said patterned conducting layer on said substrate; baking said first spin-on-glass layer at an elevated temperature, and out gassing said first spin-on-glass layer; coating a second spin-on-glass layer on said first spin-on-glass layer, dispensed at a second and constant spin speed greater than the first spin-speed and thereby filling completely said recesses formed by said patterned conducting layer and forming an essentially planar second spin-on-glass layer over said patterned conducting layer; curing said second spin-on-glass layer at an elevated temperature to pyrolize said second spin-on-layer forming an inorganic glass layer and completing said planar glass layer over patterned conducting layer.
Claim 2
Independent Claim
188 words
A method for forming a planarized dielectric layer over a substrate having a patterned conducting layer comprising the steps of: providing a semiconductor substrate having semiconductor devices formed in and on said substrate and having a patterned conducting layer formed thereon; depositing an insulating layer on said semiconductor devices and said patterned conducting layer; coating said insulating layer with a first spin-on-glass layer dispensed at a first and constant spin speed of between about 600 to 800 revolutions per minute (rpm) and thereby partially filling recesses formed by said patterned conducting layer on said substrate; baking said first spin-on-glass layer at an elevated temperature, and out gassing said first spin-on-glass layer; coating a second spin-on-glass layer on said first spin-on-glass layer, dispensed at a second and constant spin speed greater than the first spin-speed and thereby filling completely said recesses formed by said patterned conducting layer and forming an essentially planar second spin-on-glass layer over said patterned conducting layer; curing said second spin-on-glass layer at an elevated temperature to pyrolize said second spin-on-layer forming an inorganic glass layer and completing said planar glass layer over patterned conducting layer.
Claim 3
Dependent Claim
27 words
The method of claim 1, wherein said insulating layer is deposited by plasma enhanced chemical vapor deposition and having a thickness from about 2000 to 4000 Angstroms.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein said first spin-on-glass is dispensed for about 6 seconds and dried for 15 seconds at said spin speed at about 25° C.
Claim 5
Dependent Claim
33 words
The method of claim 3, wherein said first spin-on-glass layer is baked at a temperature of between about 100° to 300° C. and having a thickness range of about 2000 to 4000 Angstroms.
Claim 6
Dependent Claim
45 words
The method of claim 1, wherein said second spin-on-glass layer is dispensed at a second wafer spin speed of between about 2500 to 3000 revolutions per minute (rpm) for about 6 seconds and dried for 15 seconds at zero spin speed at about 25° C.
Claim 7
Dependent Claim
33 words
The method of claim 5, wherein said second spin-on-glass layer is cured at a temperature of between about 100° to 300° C. and having a thickness range of about 2000 to 2500 Angstroms.
Claim 8
Dependent Claim
17 words
The method of claim 1, wherein said first and second spin-on-glass layers are of the siloxane type.
Claim 9
Independent Claim
192 words
A method for forming a planarized dielectric layer over a substrate having a patterned conducting layer comprising the steps of: providing a semiconductor substrate having semiconductor field effect transistors formed in and on said substrate and having a patterned conducting layer formed thereon; depositing an insulating layer on said semiconductor devices and said patterned conducting layer; coating said insulating layer with a first spin-on-glass layer dispensed at a first and constant spin speed of between about 600 and 800 revolutions per minute (rpm) and thereby partially filling recesses formed by said patterned conducting layer on said substrate; baking said first spin-on-glass layer at an elevated temperature, thereby out gassing said first spin-on-glass layer; coating a second spin-on-glass layer on said first spin-on-glass layer, dispensed at a second and constant spin speed greater than the first spin speed and thereby filling completely said recesses formed by said patterned conducting layer and forming an essentially planar silicon oxide surface over said patterned conducting layer; curing said second spin-on-glass layer at an elevated temperature to pyrolize said second spin-on-layer forming an inorganic glass layer and completing said planar glass layer over said patterned conducting layer.
Claim 10
Independent Claim
192 words
A method for forming a planarized dielectric layer over a substrate having a patterned conducting layer comprising the steps of: providing a semiconductor substrate having semiconductor field effect transistors formed in and on said substrate and having a patterned conducting layer formed thereon; depositing an insulating layer on said semiconductor devices and said patterned conducting layer; coating said insulating layer with a first spin-on-glass layer dispensed at a first and constant spin speed of between about 600 and 800 revolutions per minute (rpm) and thereby partially filling recesses formed by said patterned conducting layer on said substrate; baking said first spin-on-glass layer at an elevated temperature, thereby out gassing said first spin-on-glass layer; coating a second spin-on-glass layer on said first spin-on-glass layer, dispensed at a second and constant spin speed greater than the first spin speed and thereby filling completely said recesses formed by said patterned conducting layer and forming an essentially planar silicon oxide surface over said patterned conducting layer; curing said second spin-on-glass layer at an elevated temperature to pyrolize said second spin-on-layer forming an inorganic glass layer and completing said planar glass layer over said patterned conducting layer.
Claim 11
Dependent Claim
27 words
The method of claim 8, wherein said insulating layer is deposited by plasma enhanced chemical vapor deposition and having a thickness from about 4000 to 6000 Angstroms.
Claim 12
Dependent Claim
29 words
The method of claim 8, wherein said first spin-on-glass layer is dispensed for about 6 seconds and dried for 15 seconds at said spin speed at about 25° C.
Claim 13
Dependent Claim
34 words
The method of claim 10, wherein said first spin-on-glass layer is baked at a temperature of between about 100° to 300° C. and having a thickness range of between about 4000 to 6000 Angstroms.
Claim 14
Dependent Claim
45 words
The method of claim 8, wherein said second spin-on-glass layer is dispensed at a second wafer spin speed of between about 2500 to 3000 revolutions per minute (rpm) for about 6 seconds and dried for 15 seconds at zero spin speed at about 25° C.
Claim 15
Dependent Claim
34 words
The method of claim 12, wherein said second spin-on-glass layer is cured at a temperature of between about 100° to 300° C. and having a thickness range of between about 2000 to 2500 Angstroms.
Claim 16
Dependent Claim
17 words
The method of claim 8, wherein said first and second spin-on-glass layers are of the siloxane type.
Claim 17
Independent Claim
195 words
A method for forming a planarized dielectric layer over a substrate having at least one patterned conducting layer comprising the steps of: providing a semiconductor substrate having bipolar transistors formed in and on said substrate and having at least one patterned conducting layer formed thereon; depositing an insulating layer on said semiconductor devices and said patterned conducting layer; coating said insulating layer with a first spin-on-glass layer dispensed at a first and constant spin speed of between about 600 to 800 revolutions per minute (rpm); and thereby partially filling recesses formed by said patterned conducting layer on said substrate; baking said first spin-on-glass layer at an elevated temperature, and out gassing said first spin-on glass layer; coating a second spin-on-glass layer on said first spin-on-glass layer, dispensed at a second and constant spin speed greater than the first spin speed and thereby filling completely said recesses formed by said patterned conducting layer and forming an essentially planar second spin-on-glass layer over said patterned conducting layer; curing said second spin-on-glass layer at an elevated temperature to pyrolize said second spin-on-glass layer forming an inorganic glass layer and completing said planar glass layer over patterned conducting layer.
Claim 18
Independent Claim
195 words
A method for forming a planarized dielectric layer over a substrate having at least one patterned conducting layer comprising the steps of: providing a semiconductor substrate having bipolar transistors formed in and on said substrate and having at least one patterned conducting layer formed thereon; depositing an insulating layer on said semiconductor devices and said patterned conducting layer; coating said insulating layer with a first spin-on-glass layer dispensed at a first and constant spin speed of between about 600 to 800 revolutions per minute (rpm); and thereby partially filling recesses formed by said patterned conducting layer on said substrate; baking said first spin-on-glass layer at an elevated temperature, and out gassing said first spin-on glass layer; coating a second spin-on-glass layer on said first spin-on-glass layer, dispensed at a second and constant spin speed greater than the first spin speed and thereby filling completely said recesses formed by said patterned conducting layer and forming an essentially planar second spin-on-glass layer over said patterned conducting layer; curing said second spin-on-glass layer at an elevated temperature to pyrolize said second spin-on-glass layer forming an inorganic glass layer and completing said planar glass layer over patterned conducting layer.
Claim 19
Dependent Claim
28 words
The method of claim 15, wherein said insulating layer is deposited by plasma enhanced chemical vapor deposition and having a thickness from between about 2000 to 4000 Angstroms.
Claim 20
Dependent Claim
28 words
The method of claim 15, wherein said first spin-on-glass is dispensed for about 6 seconds and dried for 15 seconds at said spin speed at about 25° C.
Claim 21
Dependent Claim
34 words
The method of claim 17, wherein said first spin-on-glass layer is baked at a temperature of between about 100° to 300° C. and having a thickness range of between about 2000 to 4000 Angstroms.
Claim 22
Dependent Claim
45 words
The method of claim 15, wherein said second spin-on-glass layer is dispensed at a second wafer spin speed of between about 2500 to 3000 revolutions per minute (rpm) for about 6 seconds and dried for 15 seconds at zero spin speed at about 25° C.
Claim 23
Dependent Claim
34 words
The method of claim 19, wherein said second spin-on-glass layer is cured at a temperature of between about 100° to 300° C. and having a thickness range of between about 2000 to 2500 Angstroms.
Claim 24
Dependent Claim
17 words
The method of claim 15, wherein said first and second spin-on-glass layers are of the siloxane type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-25 | 1999-03-27 | 1999-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-25 | 2003-03-27 | 2003-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-25 | 2007-03-27 | 2007-09-26 | $7700.00 | Window Closed / Lapsed |