Method of eliminating degradation of a multilayer metallurgy/insulator structure of a VLSI integrated circuit

Claim 1

A method for forming multiple metal, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion comprising: providing a semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within said semiconductor substrate electrically separating certain of these source/drain regions from one another; forming a first passivation layer over the surfaces of said patterns; and forming said multilayer metallurgy thereover by opening a pattern of openings through said passivation layer to at least some of said source/drain regions, depositing and patterning a first metallurgy layer in contact with said pattern of openings; forming a first silicon oxide via dielectric layer over said pattern of first metallurgy layer; forming a spin-on-glass layer over said via dielectric layer and curing the layer; forming a second silicon oxide via dielectric layer over said spin-on-glass layer; forming a pattern of openings in said second via layer, said spin-on-glass layer, and said first via layer; depositing and patterning a second metallurgy layer in contact with said pattern of openings to make electrical contact with said first metallurgy layer; forming a second passivating dielectric layer over said second metallurgy layer; and illuminating the structure with ultra violet radiation for a time sufficient to neutralize charges in the multilevel metallurgy structure wherein said multilevel metallurgy integrated circuit with substantially free field inversion is completed.

Claim 2

A method for forming multiple metal, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion comprising: providing a semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within said semiconductor substrate electrically separating certain of these source/drain regions from one another; forming a first passivation layer over the surfaces of said patterns; and forming said multilayer metallurgy thereover by opening a pattern of openings through said passivation layer to at least some of said source/drain regions, depositing and patterning a first metallurgy layer in contact with said pattern of openings; forming a first silicon oxide via dielectric layer over said pattern of first metallurgy layer; forming a spin-on-glass layer over said via dielectric layer and curing the layer; forming a second silicon oxide via dielectric layer over said spin-on-glass layer; forming a pattern of openings in said second via layer, said spin-on-glass layer, and said first via layer; depositing and patterning a second metallurgy layer in contact with said pattern of openings to make electrical contact with said first metallurgy layer; forming a second passivating dielectric layer over said second metallurgy layer; and illuminating the structure with ultra violet radiation for a time sufficient to neutralize charges in the multilevel metallurgy structure wherein said multilevel metallurgy integrated circuit with substantially free field inversion is completed.

Claim 13

A method of substantially eliminating degradation of semiconductor devices and structures within a multilayer metallurgy structure, caused by plasma enhanced process steps used in fabrication of the devices which result in unwanted positive charges comprising; providing a semiconductor substrate having said semiconductor devices and structures within a multilayer metallurgy structure wherein there is a multilayer insulating layer between two layers of metallurgy which insulating layer includes a first layer of silicon oxide, a spin-on-glass layer and a second layer of silicon oxide; subjecting the devices to a process step that exposes it to a plasma environment which introduces said positive charges in a polysilicon resistor which is part of said semiconductor devices; illuminating the structure with ultra violet radiation for a time sufficient to neutralize said positive charges in the said polysilicon resistor to thereby overcome the degradation.

Claim 14

A method of substantially eliminating degradation of semiconductor devices and structures within a multilayer metallurgy structure, caused by plasma enhanced process steps used in fabrication of the devices which result in unwanted positive charges comprising; providing a semiconductor substrate having said semiconductor devices and structures within a multilayer metallurgy structure wherein there is a multilayer insulating layer between two layers of metallurgy which insulating layer includes a first layer of silicon oxide, a spin-on-glass layer and a second layer of silicon oxide; subjecting the devices to a process step that exposes it to a plasma environment which introduces said positive charges in a polysilicon resistor which is part of said semiconductor devices; illuminating the structure with ultra violet radiation for a time sufficient to neutralize said positive charges in the said polysilicon resistor to thereby overcome the degradation.