US5494853A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method to solve holes in passivation by metal layout
Assignee: United Microelectronics Corp
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Filing: 1994-07-25
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Granted: 1996-02-27
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Expires: 2014-07-25
Abstract
Abstract A new method of forming the passivation layer of an integrated circuit using metal layout is described. An insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. Metal lines are formed having a metal line layout in which the metal lines have a fixed spacing throughout their length and larger width around a turn than they have throughout the remainder of their length. Metal islands are formed perpendicular to the metal lines at the terminals of the metal lines. Dummy vias are opened in the insulating layer at the terminals of the metal lines wherein the terminals of the metal lines fill the dummy vias thereby reducing the aspect ratio of the spacing of said metal lines. A passivation layer is deposited over the metal lines wherein tunnels are formed within the passivation layer between the metal lines and at the terminals of the metal lines. The metal layout of the present invention prevents openings from being made within the passivation layer to the tunnels. The passivation layer is covered with a resist layer. The resist layer has a relatively constant thickness because the resist does not sink into the tunnels. The passivation layer is patterned. Holes are not formed within the passivation layer because of the relatively constant thickness of the resist layer.
Inventors
- 👤 Water Lur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:17
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/131; H10W74/137; H10W20/00; H10W20/01; H10W20/031; H10W20/40; H10W20/41; H10W20/43; Y; Y10; Y10S; Y10S148/00; Y10S148/137; Y10S438/00; Y10S438/926; Y10S438/958
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
243 words
The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising: providing an insulating layer over semiconductor device structures in and on a semiconductor substrate; forming metal lines having a metal line layout comprising: said metal lines have a fixed spacing throughout the length of said metal lines; said metal lines have a larger width around a turn than they have throughout the remainder of their length; metal islands are formed perpendicular to said metal lines at the terminals of said metal lines; and dummy vias are opened in said insulating layer at the terminals of said metal lines wherein said terminals of said metal lines fill said dummy vias thereby reducing the aspect ratio of said spacing of said metal lines; depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer between said metal lines and at the terminals of said metal lines and wherein said metal layout prevents openings from being made within said passivation layer to said tunnels; covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels; patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer; and removing said resist layer to complete said fabrication of said integrated circuit.
Claim 2
Independent Claim
243 words
The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising: providing an insulating layer over semiconductor device structures in and on a semiconductor substrate; forming metal lines having a metal line layout comprising: said metal lines have a fixed spacing throughout the length of said metal lines; said metal lines have a larger width around a turn than they have throughout the remainder of their length; metal islands are formed perpendicular to said metal lines at the terminals of said metal lines; and dummy vias are opened in said insulating layer at the terminals of said metal lines wherein said terminals of said metal lines fill said dummy vias thereby reducing the aspect ratio of said spacing of said metal lines; depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer between said metal lines and at the terminals of said metal lines and wherein said metal layout prevents openings from being made within said passivation layer to said tunnels; covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels; patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer; and removing said resist layer to complete said fabrication of said integrated circuit.
Claim 3
Dependent Claim
30 words
The method of claim 1 wherein said dummy vias are formed without a dogbone layout and wherein said dummy vias do not extend all the way through said insulating layer.
Claim 4
Independent Claim
182 words
The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising: providing an insulating layer over semiconductor device structures in and on a semiconductor substrate; forming metal lines having a metal line layout wherein said metal lines have a fixed spacing throughout the length of said metal lines and wherein said metal lines have a larger width around a turn than they have throughout the remainder of their length; depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer between said metal lines and wherein said metal layout prevents openings from being made within said passivation layer to said tunnels; covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels; patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer; and removing said resist layer to complete said fabrication of said integrated circuit.
Claim 5
Independent Claim
182 words
The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising: providing an insulating layer over semiconductor device structures in and on a semiconductor substrate; forming metal lines having a metal line layout wherein said metal lines have a fixed spacing throughout the length of said metal lines and wherein said metal lines have a larger width around a turn than they have throughout the remainder of their length; depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer between said metal lines and wherein said metal layout prevents openings from being made within said passivation layer to said tunnels; covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels; patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer; and removing said resist layer to complete said fabrication of said integrated circuit.
Claim 6
Independent Claim
208 words
The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising: providing an insulating layer over semiconductor device structures in and on a semiconductor substrate; forming metal lines having a metal line layout wherein said metal lines have a fixed spacing throughout the length of said metal lines and wherein said metal lines have a larger width around a turn than they have throughout the remainder of their length and wherein metal islands are formed perpendicular to said metal lines at the terminals of said metal lines; depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer between said metal lines and at the terminals of said metal lines and wherein said metal layout prevents openings from being made within said passivation layer to said tunnels; covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels; patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer; and removing said resist layer to complete said fabrication of said integrated circuit.
Claim 7
Independent Claim
208 words
The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising: providing an insulating layer over semiconductor device structures in and on a semiconductor substrate; forming metal lines having a metal line layout wherein said metal lines have a fixed spacing throughout the length of said metal lines and wherein said metal lines have a larger width around a turn than they have throughout the remainder of their length and wherein metal islands are formed perpendicular to said metal lines at the terminals of said metal lines; depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer between said metal lines and at the terminals of said metal lines and wherein said metal layout prevents openings from being made within said passivation layer to said tunnels; covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels; patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer; and removing said resist layer to complete said fabrication of said integrated circuit.
Claim 8
Independent Claim
186 words
The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising: providing an insulating layer over semiconductor device structures in and on a semiconductor substrate; opening dummy vias in said insulating layer at the terminals of planned metal lines; forming metal lines overlying said insulating layer wherein said terminals of said metal lines fill said dummy vias thereby reducing the aspect ratio of the spacing of said metal lines; depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer at the terminals of said metal lines and wherein said reduced aspect ratio prevents openings from being made within said passivation layer to said tunnels; covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels; patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer; and removing said resist layer to complete said fabrication of said integrated circuit.
Claim 9
Independent Claim
186 words
The method of metal line layout to prevent the formation of holes in an overlying passivation layer in the fabrication of an integrated circuit comprising: providing an insulating layer over semiconductor device structures in and on a semiconductor substrate; opening dummy vias in said insulating layer at the terminals of planned metal lines; forming metal lines overlying said insulating layer wherein said terminals of said metal lines fill said dummy vias thereby reducing the aspect ratio of the spacing of said metal lines; depositing a passivation layer over said metal lines wherein tunnels are formed within said passivation layer at the terminals of said metal lines and wherein said reduced aspect ratio prevents openings from being made within said passivation layer to said tunnels; covering said passivation layer with a resist layer wherein said resist layer has a relatively constant thickness because said resist does not sink into said tunnels; patterning said passivation layer wherein holes are not formed within said passivation layer because of said relatively constant thickness of said resist layer; and removing said resist layer to complete said fabrication of said integrated circuit.
Claim 10
Dependent Claim
30 words
The method of claim 5 wherein said dummy vias are formed without a dogbone layout and wherein said dummy vias do not extend all the way through said insulating layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |