US5631478A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuits with specific pitch multilevel interconnections
Assignee: NEC Corp
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Filing: 1994-12-15
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Granted: 1997-05-20
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Expires: 2014-12-15
Abstract
Abstract A multilevel interconnection structure for semiconductor integrated circuits has five or more multiple interconnection layers, each of which includes a plurality of interconnections, wherein the lower level interconnections included in first to third interconnection layers form the lowest level interconnection layer have pitches less than 2 micrometers and the high level interconnections included in the remaining interconnection layers have pitches in the range from 2 to 3 micrometers.
Inventors
- 👤 Koichiro Okumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:34
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/435; H10W20/44; H10W20/4403; H10W20/4421
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
107 words
A multilevel interconnection structure for semiconductor integrated circuits, said structure comprising at least five interconnection layer levels, each of said layers including interconnections at each level, wherein first, second and third lowest level interconnections have a first uniform pitch and are so provided in first, second and third lowest level interconnection layers as to have pitches less than approximately 2 micrometers and ranging from 4.5 to 5.5 times a minimum gate length of MOS field effect transistors of said semiconductor integrated circuits, and remaining higher level interconnections in remaining higher level interconnection layers have a second uniform pitch ranging from approximately 2 micrometers to approximately 3 micrometers.
Claim 2
Dependent Claim
107 words
A multilevel interconnection structure for semiconductor integrated circuits, said structure comprising at least five interconnection layer levels, each of said layers including interconnections at each level, wherein first, second and third lowest level interconnections have a first uniform pitch and are so provided in first, second and third lowest level interconnection layers as to have pitches less than approximately 2 micrometers and ranging from 4.5 to 5.5 times a minimum gate length of MOS field effect transistors of said semiconductor integrated circuits, and remaining higher level interconnections in remaining higher level interconnection layers have a second uniform pitch ranging from approximately 2 micrometers to approximately 3 micrometers.
Claim 3
Dependent Claim
13 words
The structure as claimed in claim 1, wherein said interconnections are made aluminium.
Claim 4
Dependent Claim
14 words
The structure as claimed in claim 1, wherein said interconnections are made of copper.
Claim 5
Dependent Claim
113 words
The structure as claimed in claim 3, wherein said structure comprises five interconnection layers level comprising: a first lowest level interconnection layer provided on a first inter-layer insulator on a semiconductor substrate ; a second lowest interconnection layer provided on a second inter-layer insulator provided on said first lowest level interconnection layer; a third lowest level interconnection layer provided on a third inter-layer insulator provided on said second lowest level interconnection layer ; a fourth lowest level interconnection layer provided on a fourth inter-layer insulator provided on said third lowest level interconnection layer ; and a fifth lowest level interconnection layer provided on a fifth inter-layer insulator provided on said fourth interconnection layer.
Claim 6
Dependent Claim
138 words
A multilevel interconnection structure for semiconductor integrated circuits, said structure comprising a plurality of interconnection groups having various levels, wherein a higher level interconnection group has a larger pitch and a larger width than an adjacent lower level interconnection group, said structure comprising at least five level interconnection groups, each of said groups including interconnections at each level, a first, second and third lowest level interconnections provided in first, second and third lowest level interconnection groups have a first uniform pitch of less than approximately 2 micrometers and in a range from 4.5 to 5.5 times of a minimum gate length of MOS field effect transistors of said semiconductor integrated circuits and remaining higher level interconnections in remaining higher level interconnection groups have a second uniform pitch in the range from approximately 2 micrometers to approximately 3 micrometers.
Claim 7
Dependent Claim
138 words
A multilevel interconnection structure for semiconductor integrated circuits, said structure comprising a plurality of interconnection groups having various levels, wherein a higher level interconnection group has a larger pitch and a larger width than an adjacent lower level interconnection group, said structure comprising at least five level interconnection groups, each of said groups including interconnections at each level, a first, second and third lowest level interconnections provided in first, second and third lowest level interconnection groups have a first uniform pitch of less than approximately 2 micrometers and in a range from 4.5 to 5.5 times of a minimum gate length of MOS field effect transistors of said semiconductor integrated circuits and remaining higher level interconnections in remaining higher level interconnection groups have a second uniform pitch in the range from approximately 2 micrometers to approximately 3 micrometers.
Claim 8
Dependent Claim
14 words
The structure as claimed in claim 5, wherein said interconnections are made or aluminium.
Claim 9
Dependent Claim
13 words
The structure as claimed in claim 5, wherein interconnections are made of cooper.
Claim 10
Dependent Claim
113 words
The structure as claimed in claim 7, wherein said structure comprises five level interconnection groups comprising : a first lowest level interconnection group provided on a first inter-layer insulator a semiconductor substrate ; a second lowest interconnection group provided on a second inter-layer insulator provided on said first lowest level interconnection group ; a third lowest level interconnection group provided on a third inter-layer insulator provided on said second lowest level interconnection group; a fourth lowest level interconnection group provided on a fourth inter-layer insulator provided on said third lowest level interconnection group ; and a fifth lowest level interconnection group provided on a fifth inter-layer insulator provided on said fourth interconnection group.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-19 | 2000-11-18 | 2001-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-19 | 2004-11-18 | 2005-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-19 | 2008-11-18 | 2009-05-20 | $7700.00 | Window Closed / Lapsed |