EP0408060A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor integrated circuit device and logic correcting method of the same
Assignee: Hitachi Ltd
•
Filing: 1990-07-13
•
Granted: —
•
Expires: 2010-07-13
Abstract
Abstract A semiconductor integrated circuit device comprises logic elements provided on a semiconductor substrate and laminated wiring layers formed by alternately laminating insulation layers (111) and wiring layers (S1 - S5) on the logic elements. The logic elements are connected by the laminated wiring layers. The laminated wiring layers are formed by a lower wiring layer (LL; S1 - S3) and an upper wiring layer (UL; S4 - S5) laid on the lower wiring layer. Part of a net connecting the logic elements includes terminals (140 - 147) in the upper wiring layer (UL) and is connected therewith. Namely, part of the net passes through the upper wiring layer (UL). The semiconductor integrated circuit device further comprises unused logic elements not connected with any other logic elements and a logic element having a disable terminal (300), wherein input/output terminals (214, 216, 218) of the unused logic element and the disable terminal (300) are led into the upper wiring layer (UL). Logic correction of the semiconductor integrated circuit device is carried out by altering connecting pattern between the terminals (140 - 147) at a part of the net using the upper wiring layer, connecting the input/output terminals (214, 216, 218) of the unused logic element with the other terminals (210a, 210b) and connecting the disable terminal (300) to the predetermined wirings. Namely, the wiring layers (S1, S2, .....) are structured in the semiconductor integrated circuit device provided with many laminated wiring layers (S1, S2, .....) so that correction of wiring layers may be realized only at the upper wiring layer UL.
Inventors
- 👤 Mitsuo Usami
- 👤 Hiroyuki Akimori
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 09:52
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10W; H10W20/00; H10W20/40; H10W20/49
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
113 words
A semiconductor integrated circuit device comprising, logic elements (G) provided on a semiconductor substrate (600) and laminated wiring layers formed by alternately laminating insulation layers (111) and wiring layers (S1, S2, .....) on said logic elements (G), said logic elements (G) being connected with said laminated wiring layers, characterized in that said each laminated wiring layer is comprised of a lower wiring layer (LL) and an upper wiring layer (UL) laid on said lower wiring layer (LL), and that a part of a net connecting the logic elements (G) passes on the upper wiring layer (UL) so as to correct wirings between the logic elements (G) only with the upper wiring layer (UL).
Claim 2
Dependent Claim
113 words
A semiconductor integrated circuit device comprising, logic elements (G) provided on a semiconductor substrate (600) and laminated wiring layers formed by alternately laminating insulation layers (111) and wiring layers (S1, S2, .....) on said logic elements (G), said logic elements (G) being connected with said laminated wiring layers, characterized in that said each laminated wiring layer is comprised of a lower wiring layer (LL) and an upper wiring layer (UL) laid on said lower wiring layer (LL), and that a part of a net connecting the logic elements (G) passes on the upper wiring layer (UL) so as to correct wirings between the logic elements (G) only with the upper wiring layer (UL).
Claim 3
Dependent Claim
34 words
The device of claim 1, wherein the net leads terminals (140 - 147) within the upper wiring layer (UL) to connect the terminals with the wirings (S4, S5) of the upper wiring layer (UL).
Claim 4
Dependent Claim
37 words
The device of claim 1 or 2, comprising an unused logic element not connected with any other logic elements, input/output terminals (214, 216, 218) of said unused logic element being led into the upper wiring layer (UL).
Claim 5
Independent Claim
28 words
The device of any one of claims 1 to 3, comprising a logic element including a disable terminal (300) which is led into the upper wiring layer (UL).
Claim 6
Independent Claim
21 words
The device of any one of claims 1 to 4, comprising a spare channel (400) within the upper wiring layer (UL).
Claim 7
Independent Claim
35 words
The device of any one of claims 2 to 5, wherein correction of the upper wiring layer (UL) is carried out by altering connections among the terminals (140 - 147, 214, 216, 218, 300, 400).
Claim 8
Independent Claim
45 words
The device of any one of claims 1 to 6, wherein said device has basic cells (604) comprising transistors on the semi-conductor substrate (600), the logic element (G) is formed by connecting between the transistors, and each transistor is a CMOS, Bi-CMOS or Bipolar transistor.
Claim 9
Independent Claim
22 words
The device of any one of claims 1 to 7, wherein the upper wiring layer (UL) comprises two or more wiring layers.
Claim 10
Independent Claim
25 words
The device of any one of claims 1 to 8, wherein the logic element (G) is a logic gate such as inverter, NAND and NOR.
Claim 11
Independent Claim
137 words
A method of logic correction for semiconductor integrated circuit device comprising logic elements (G) provided on a semiconductor substrate (600) and laminated wiring layers formed by alternately laminating insulation layers (111) and wiring layers (S1, S2, .....) on the logic elements (G), said logic elements (G) being connected with said laminated wiring layers, characterized in that said each laminated wiring layer is comprised of a lower wiring layer (LL) and an upper wiring layer (UL) laid on said lower wiring layer, that a part of net connecting the logic elements (G) has terminals (140 - 147) in the upper wiring layers (UL), said terminals being connected <520> with the upper wiring layer (UL), and that correction of connections between the logic elements (G) is carried out by altering connections between terminals with the upper wiring layer <533>.
Claim 12
Independent Claim
137 words
A method of logic correction for semiconductor integrated circuit device comprising logic elements (G) provided on a semiconductor substrate (600) and laminated wiring layers formed by alternately laminating insulation layers (111) and wiring layers (S1, S2, .....) on the logic elements (G), said logic elements (G) being connected with said laminated wiring layers, characterized in that said each laminated wiring layer is comprised of a lower wiring layer (LL) and an upper wiring layer (UL) laid on said lower wiring layer, that a part of net connecting the logic elements (G) has terminals (140 - 147) in the upper wiring layers (UL), said terminals being connected <520> with the upper wiring layer (UL), and that correction of connections between the logic elements (G) is carried out by altering connections between terminals with the upper wiring layer <533>.
Claim 13
Dependent Claim
61 words
The method of claim 10, wherein said device comprises an unused logic element not connected with any other logic elements, input/output terminals (214, 216, 218) of said unused logic element are led into the upper wiring layer (UL), and correction of connection between the logic terminals (G) is carried out by connecting the input/output terminals (214, 216, 218) and said terminals.
Claim 14
Dependent Claim
46 words
The method of claim 10 or 11, wherein said device com prises a logic element including a disable terminal (300) which is led into the upper wiring layer (UL) and correction of logic is carried out by connecting said disable terminal (300) to the predetermined wirings.
Claim 15
Independent Claim
22 words
The method of any one of claims 10 to 12, wherein said upper wiring layer (UL) comprises two or more wiring layers.
Claim 16
Independent Claim
41 words
The method of any one of claims 10 to 13, wherein correction of said upper wiring layer (UL) is carried out by previously forming wiring layers from the upper layer to lower layer and using a mask depending on specifications <540>.
Claim 17
Independent Claim
37 words
The method of any one of claims 10 to 13, wherein correction of said upper wiring layer (UL) is carried out by disconnecting and connecting local wirings after wiring layers up to the uppermost layer are formed.
Claim 18
Independent Claim
27 words
The method of any one of claims 10 to 15, wherein connections between said terminals (140 - 147) are carried out by automatic layout and wiring system.
Claim 19
Independent Claim
28 words
The method of any one of claims 10 to 16, wherein alteration of connecting pattern between the terminals is carried out by the automatic layout and wiring system.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.