EP0525824A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A semiconductor device having metal wiring layers and method of manufacturing such a device
Assignee: Fujitsu Ltd
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Filing: 1988-08-17
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Granted: —
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Expires: 2008-08-17
Abstract
Abstract A semiconductor device comprising a semiconductor substrate (1); a plurality of metal wiring layers (31, 32, 33, 34) formed over said semiconductor substrate, the metal wiring layers comprising one or more lower side metal wiring layers (31, 32) having a small width and one or more upper side metal wiring layers (33, 34) having a large width; a respective first insulation layer (41, 42) formed on each of the lower side metal wiring layers (31, 32), each first insulation layer having a contracting characteristic relative to said substrate; and a respective second insulation layer (43, 44) formed on each of the upper side metal wiring layers (33, 34), each second insulation layer being formed by a compressive stress insulation layer having an expanding characteristic relative to said substrate. The layer structure prevents the generation of cracks in the insulation layers. <IMAGE>
Inventors
- 👤 Junichi Itoh
- 👤 Kazuyuki Kurita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 13:02
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/662; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10W; H10W20/00; H10W20/01; H10W20/40; H10W20/41; H10W20/43; H10W20/45; H10W20/48; H10P14/6336; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/6923; H10P14/6927; H10P14/694; H10P14/6943; H10P14/69433
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
135 words
A semiconductor device comprising:- a semiconductor substrate (1); a plurality of metal wiring layers (31, 32, 33, 34) formed over said semiconductor substrate, said plurality of metal wiring layers comprising one or more lower side metal wiring layers (31, 32) having a first width and one or more upper side metal wiring layers (33, 34) having a second width larger than said first width; a respective first insulation layer (41, 42) formed on each of the lower side metal wiring layers (31, 32), each first insulation layer having a contracting characteristic relative to said substrate; and a respective second insulation layer (43, 44) formed on each of the upper side metal wiring layers (33, 34), each second insulation layer being formed by a compressive stress insulation layer having an expanding characteristic relative to said substrate.
Claim 2
Dependent Claim
135 words
A semiconductor device comprising:- a semiconductor substrate (1); a plurality of metal wiring layers (31, 32, 33, 34) formed over said semiconductor substrate, said plurality of metal wiring layers comprising one or more lower side metal wiring layers (31, 32) having a first width and one or more upper side metal wiring layers (33, 34) having a second width larger than said first width; a respective first insulation layer (41, 42) formed on each of the lower side metal wiring layers (31, 32), each first insulation layer having a contracting characteristic relative to said substrate; and a respective second insulation layer (43, 44) formed on each of the upper side metal wiring layers (33, 34), each second insulation layer being formed by a compressive stress insulation layer having an expanding characteristic relative to said substrate.
Claim 3
Dependent Claim
36 words
A semiconductor device according to claim 1, wherein said lower side metal wiring layers (31, 32) are used as signal lines and said upper side metal wiring layers (33, 34) are used as power supply lines.
Claim 4
Dependent Claim
54 words
A semiconductor device according to claim 1 or 2, wherein there are four said metal wiring layers (31, 32, 33, 34), of which first and second metal wiring layers (31, 32) are the lower side metal wiring layers, and third and fourth metal wiring layers (33, 34) are the upper side metal wiring layers.
Claim 5
Independent Claim
142 words
A method of manufacturing a semiconductor device, comprising steps of:- forming a plurality of metal wiring layers (31, 32, 33, 34) over a semiconductor substrate, said plurality of metal wiring layers comprising one or more lower side metal wiring layers (31, 32) having a first width and one or more upper side metal wiring layers (33, 34) having a second width larger than said first width; forming a respective first insulation layer (41, 42) on each of the lower side metal wiring layers (31, 32) by thermal chemical vapor deposition or plasma assisted chemical vapor deposition which is performed at a discharge frequency higher than 2 MHz; and forming respective second insulation layers (43, 44) on each of the upper side metal wiring layers (33, 34) by plasma-assisted chemical vapor deposition which is performed at a discharge frequency lower than 2 MHz.
Claim 6
Independent Claim
142 words
A method of manufacturing a semiconductor device, comprising steps of:- forming a plurality of metal wiring layers (31, 32, 33, 34) over a semiconductor substrate, said plurality of metal wiring layers comprising one or more lower side metal wiring layers (31, 32) having a first width and one or more upper side metal wiring layers (33, 34) having a second width larger than said first width; forming a respective first insulation layer (41, 42) on each of the lower side metal wiring layers (31, 32) by thermal chemical vapor deposition or plasma assisted chemical vapor deposition which is performed at a discharge frequency higher than 2 MHz; and forming respective second insulation layers (43, 44) on each of the upper side metal wiring layers (33, 34) by plasma-assisted chemical vapor deposition which is performed at a discharge frequency lower than 2 MHz.
Claim 7
Dependent Claim
56 words
A method of manufacturing a semiconductor device according to claim 4, wherein there are four said metal wiring layers (31, 32, 33, 34), of which first and second metal wiring layers (31, 32) are the lower side metal wiring layers, and third and fourth metal wiring layers (33, 34) are the upper side metal wiring layers.
References Cited (Backward Citations)
No citation records indexed.
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