US5266525A
Expired / Lapsed
US
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Microelectronic interlayer dielectric structure and methods of manufacturing same
Assignee: Seiko Epson Corp
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Filing: 1991-08-07
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Granted: 1993-11-30
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Expires: 2011-08-07
Abstract
Abstract A method of manufacturing an interlayer dielectric for microelectronic devices having multiple conducting layers provides a planarized surface for deposition of subsequent layers and further prevents cracking of spin-on-glass by limiting spin-on-glass thickness to about 0.4 μm or less. A first dielectric layer is formed over a first conducting layer by means of reacting Si(OC 2 H 5 ) 4 and O 2 at approximately 9 torr between 370° C. to 400° C., and a second dielectric layer is formed over the first dielectric layer by a method different than that used to form the first dielectric layer. After etching back the second dielectric layer, a spin-on-glass layer is formed. Spin-on-glass layer is etched back to provide a planar surface and a third dielectric layer is formed over the spin-on-glass layer. The resulting surface is ready for contact hole formation, deposition and patterning of subsequent conductive and insulating layers.
Inventors
- 👤 Yukio Morozumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:55
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10W20/092; Y; Y10; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917; Y10T428/24926
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
130 words
A method of manufacturing a microelectronic dielectric structure comprising the steps of: a) forming a first dielectric layer by a first film growth process; b) forming a second dielectric layer, on top of said first dielectric layer, by a second film growth process wherein said step of forming said second dielectric layer comprises reacting Si(OC 2 H 5 ) 4 and O 3 with an O 2 carrier at 60 to 100 torr and approximately 380° C.; c) etching said second dielectric layer until said first dielectric layer is exposed; d) forming a layer of spin-on-glass over the surface of said first and second dielectrics; e) etching said spin-on-glass layer until the surface has been planarized; and f) forming a third dielectric layer, on top of said second dielectric layer.
Claim 2
Independent Claim
130 words
A method of manufacturing a microelectronic dielectric structure comprising the steps of: a) forming a first dielectric layer by a first film growth process; b) forming a second dielectric layer, on top of said first dielectric layer, by a second film growth process wherein said step of forming said second dielectric layer comprises reacting Si(OC 2 H 5 ) 4 and O 3 with an O 2 carrier at 60 to 100 torr and approximately 380° C.; c) etching said second dielectric layer until said first dielectric layer is exposed; d) forming a layer of spin-on-glass over the surface of said first and second dielectrics; e) etching said spin-on-glass layer until the surface has been planarized; and f) forming a third dielectric layer, on top of said second dielectric layer.
Claim 3
Dependent Claim
17 words
The method of claim 1 wherein said first, second and third dielectric films are silicon oxide films.
Claim 4
Independent Claim
206 words
A method for manufacturing a microelectronic device having multiple conductive layers separated by a complex dielectric structure, comprising the steps of: a) depositing a first conductive layer on said microelectronic device; b) patterning said first conductive layer to form a plurality of individual conductive lines; c) forming a first dielectric layer over said conductive lines by a first film growth process; d) forming a second dielectric layer, on top of said first dielectric layer, by a second film growth process wherein said step of forming said second dielectric layer comprises reacting Si(OC 2 H 5 ) 4 and O 3 with an O 2 carrier at 60 to 100 torr and approximately 380° C.; e) etching said second dielectric layer until a portion of said first dielectric layer is exposed; f) forming a layer of spin-on-glass over the surface of said first and second dielectric layers; g) etching said spin-on-glass layer until the surface has been planarized; h) forming a third dielectric layer, on top of said second dielectric layer, by said first film growth process; i) etching contact holes through said third and first dielectric layers; and j) depositing a second conductive layer on the surface comprising said third dielectric layer and said contact holes.
Claim 5
Independent Claim
206 words
A method for manufacturing a microelectronic device having multiple conductive layers separated by a complex dielectric structure, comprising the steps of: a) depositing a first conductive layer on said microelectronic device; b) patterning said first conductive layer to form a plurality of individual conductive lines; c) forming a first dielectric layer over said conductive lines by a first film growth process; d) forming a second dielectric layer, on top of said first dielectric layer, by a second film growth process wherein said step of forming said second dielectric layer comprises reacting Si(OC 2 H 5 ) 4 and O 3 with an O 2 carrier at 60 to 100 torr and approximately 380° C.; e) etching said second dielectric layer until a portion of said first dielectric layer is exposed; f) forming a layer of spin-on-glass over the surface of said first and second dielectric layers; g) etching said spin-on-glass layer until the surface has been planarized; h) forming a third dielectric layer, on top of said second dielectric layer, by said first film growth process; i) etching contact holes through said third and first dielectric layers; and j) depositing a second conductive layer on the surface comprising said third dielectric layer and said contact holes.
Claim 6
Dependent Claim
27 words
The method of claim 3 wherein said first conductive layer is a material selected from the group consisting of Al, Al-Si, Al-Si-Cu, polysilicon, metal silicides, and TiN.
Claim 7
Dependent Claim
27 words
The method of claim 3 wherein said second conductive layer is a material selected from the group consisting of Al, Al-Si, Al-Si-Cu, polysilicon, metal silicides, and TiN.
Claim 8
Dependent Claim
14 words
The method of claim 3 wherein said microelectronic device is a CMOS integrated circuit.
Claim 9
Dependent Claim
26 words
The method of claim 3 wherein said step of depositing a first conductive layer comprises sputtering an Al-Cu alloy to a thickness of approximately 0.6 μm.
Claim 10
Dependent Claim
30 words
The method of claim 3 wherein said step of patterning comprises etching said first conductive layer so that the minimum spacing between conductive lines is approximately 0.5 μm or less.
Claim 11
Dependent Claim
35 words
The method of claim 3 wherein said step of forming said first dielectric layer comprises reacting Si(OC 2 H 5 ) 4 and O 2 at approximately 9 torr between 370° C. to 400° C.
Claim 12
Dependent Claim
29 words
The method of claim 3 further comprising the step of annealing for approximately 30 minutes in a N 2 atmosphere at approximately 400° C., after forming said spin-on-glass layer.
Claim 13
Dependent Claim
32 words
The method of claim 3 wherein said step of etching said spin-on-glass comprises sputter etching with a high frequency bias of 400 W in an Ar atmosphere at approximately 1×10 -4 torr.
Claim 14
Dependent Claim
21 words
The method of claim 3 wherein said step of etching said spin-on-glass is performed in an etch system with low selectivity.
Claim 15
Dependent Claim
15 words
The method of claim 3 wherein said step of etching said spin-on-glass comprises ion milling.
Claim 16
Dependent Claim
16 words
The method of claim 3 wherein said third dielectric layer is grown to approximately 1,000 Å.
Claim 17
Dependent Claim
52 words
The method of claim 3 wherein said step of etching said contact holes comprises the steps of: a) wet etching said third and first dielectric layers to a collective depth of approximately 2,500 Å with an aqueous solution of HF and NH 4 F; and b) dry etching the remaining first dielectric.
Claim 18
Dependent Claim
33 words
The method of claim 15 wherein said step of dry etching said remaining first dielectric is performed under a pressure of approximately 300 mtorr using CHF 3 , CF 4 and He gas.
References Cited (Backward Citations)
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| 7.5 Years (Year 8) | 2000-11-29 | 2001-05-31 | 2001-11-30 | $3760.00 | Window Closed / Lapsed |
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