Patent US5977791A successfully refreshed from Google Patents.
US5977791A
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Embedded memory block with FIFO mode for programmable logic device
Assignee: Altera Corp
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Filing: 1997-04-14
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Granted: 1999-11-02
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Expires: 2017-04-14
Abstract
Abstract An programmable logic device has an enhanced embedded array block for the efficient implementation of logic functions including a random access memory and a first-in, first-out memory. A read address register and a write address register are implemented within the embedded array block. The address registers are coupled with a memory array in the embedded array block without using a resources from a programmable interconnect scheme. The first-in, first-out memory may operate as a dual-port FIFO, without cycle-sharing on the interconnect lines.
Inventors
- 👤 Kerry S. Veenstra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:07
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17748; H03K19/1776; H03K19/17704
Claims Analysis
Total Claims: 55
Claim 1
Independent Claim
149 words
A configurable logic block in a programmable logic device integrated circuit comprising: a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address each of said plurality of memory cells; a first register coupled to said address lines of said memory array, wherein in a FIFO mode, said configurable logic block operates as a first-in, first-out memory and said first register contains a write address; a second register coupled to said address lines of said memory array, wherein in said FIFO mode, said second register contains a read address; and a local interconnect having a plurality of conductors which are programmably coupled to said memory array, said first register, and said second register, wherein said first and second registers are coupled to said address lines of said memory array without passing through said local interconnect.
Claim 2
Dependent Claim
149 words
A configurable logic block in a programmable logic device integrated circuit comprising: a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address each of said plurality of memory cells; a first register coupled to said address lines of said memory array, wherein in a FIFO mode, said configurable logic block operates as a first-in, first-out memory and said first register contains a write address; a second register coupled to said address lines of said memory array, wherein in said FIFO mode, said second register contains a read address; and a local interconnect having a plurality of conductors which are programmably coupled to said memory array, said first register, and said second register, wherein said first and second registers are coupled to said address lines of said memory array without passing through said local interconnect.
Claim 3
Dependent Claim
29 words
The configurable logic block of claim 1, wherein in said FIFO mode, said first register is configured as a counter and said second register is configured as a counter.
Claim 4
Dependent Claim
56 words
The configurable logic block of claim 1 wherein said address lines of said memory array further comprise: a write address port, said write address port being coupled to said first register when in said FIFO mode; and a read address port, said read address port being coupled to said second register when in said FIFO mode.
Claim 5
Dependent Claim
60 words
The configurable logic block of claim 1 further comprising: an address input multiplexer, said first register being selectively coupled to said address lines of said memory array through said address input multiplexer during a write phase, and said second register being selectively coupled to said address lines of said memory array through said address input multiplexer during a read phase.
Claim 6
Dependent Claim
23 words
The configurable logic block of claim 4 wherein said local interconnect is selectively coupled to said address lines through said address input multiplexer.
Claim 7
Dependent Claim
71 words
The configurable logic block of claim 3 wherein said memory array further comprises: a data-in port for storing data to a write address of said memory array specified in said write address lines; and a data-out port for reading data from a read address of said memory array specified in said read address lines, wherein data is readable on said data-out port concurrently with data being stored on said data-in port.
Claim 8
Dependent Claim
25 words
The configurable logic block of claim 1 wherein said local interconnect provides control signals to said first register, said second register, and said memory array.
Claim 9
Dependent Claim
30 words
The configurable logic block of claim 7 wherein said control signals include a read enable signal, a write enable signal, a read clock, a write clock, and a reset signal.
Claim 10
Dependent Claim
29 words
The configurable logic block of claim 1 wherein said memory array is configurable with respect to a width of said memory array and a depth of said memory array.
Claim 11
Dependent Claim
25 words
The configurable logic block of claim 1 wherein a write enable input to said memory array is synchronously timed with respect to a clock signal.
Claim 12
Dependent Claim
32 words
The configurable logic block of claim 1 wherein a data input and address input to said memory array are asynchronously timed with respect to a write enable input to said memory array.
Claim 13
Dependent Claim
34 words
The configurable logic block of claim 1 wherein said first register is operable as a counter when in said FIFO mode, and as a data register in a mode other than said FIFO mode.
Claim 14
Dependent Claim
35 words
A programmable logic device comprising a plurality of configurable logic blocks as recited in claim 1, wherein said plurality of configurable logic blocks may be programmably coupled together to create a larger configurable logic block.
Claim 15
Dependent Claim
210 words
A programmable integrated circuit comprising: an interconnect grid comprising a plurality of horizontal conductors and a plurality of vertical conductors, wherein said vertical conductors may be programmably coupled to said horizontal conductors; a plurality of logic array blocks programmably coupled to said interconnect grid; and an embedded array block, programmably coupled to said interconnect grid, wherein said embedded array block is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode and comprises: a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address said memory array; a first register coupled to said address lines of said memory array, wherein said first register stores a write address when said embedded array block is in said FIFO mode; a second register coupled to said address lines of said memory array, wherein said second register stores a read address when said embedded array block is in said FIFO mode; and a local interconnect, wherein said local interconnect is programmably coupled to said interconnect grid, first register and said second register, and said first register and second register are coupled to said address lines of said memory array without passing through said local interconnect.
Claim 16
Dependent Claim
210 words
A programmable integrated circuit comprising: an interconnect grid comprising a plurality of horizontal conductors and a plurality of vertical conductors, wherein said vertical conductors may be programmably coupled to said horizontal conductors; a plurality of logic array blocks programmably coupled to said interconnect grid; and an embedded array block, programmably coupled to said interconnect grid, wherein said embedded array block is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode and comprises: a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address said memory array; a first register coupled to said address lines of said memory array, wherein said first register stores a write address when said embedded array block is in said FIFO mode; a second register coupled to said address lines of said memory array, wherein said second register stores a read address when said embedded array block is in said FIFO mode; and a local interconnect, wherein said local interconnect is programmably coupled to said interconnect grid, first register and said second register, and said first register and second register are coupled to said address lines of said memory array without passing through said local interconnect.
Claim 17
Dependent Claim
29 words
The programmable integrated circuit of claim 14 wherein when said embedded array block is in said FIFO mode, said first register and said second register are operable as counters.
Claim 18
Dependent Claim
27 words
The programmable integrated circuit of claim 15 wherein when said embedded array block is in said RAM mode, said first register is configured as a D-type register.
Claim 19
Dependent Claim
64 words
The programmable integrated circuit of claim 14 wherein said address lines of said memory array further comprise: write address lines, said write address lines being coupled to said first register when said embedded array block is in said FIFO mode; and read address lines, said read address lines being coupled to said second register when said embedded array block is in said FIFO mode.
Claim 20
Dependent Claim
54 words
The programmable integrated circuit of claim 14 further comprising: an address input multiplexer, wherein while said embedded array block is in said FIFO mode, said address input multiplexer selectively couples said address lines of said memory array to said first register during a write phase and to said second register during a read phase.
Claim 21
Dependent Claim
68 words
The programmable integrated circuit of claim 17 wherein said memory further comprises: a data-in port for storing data to a write address of said FIFO specified in said write address lines; and a data-out port for reading data from a read address of said FIFO specified in said read address lines, wherein data is readable on said data-out port concurrently with data being stored on said data-in port.
Claim 22
Dependent Claim
41 words
The programmable integrated circuit of claim 14 wherein one of said plurality of logic array blocks is configured to duplicate said first register and said second register, and to provide a status flag representative of a status of said memory array.
Claim 23
Dependent Claim
20 words
The programmable integrated circuit of claim 20 wherein said status flag is asserted when said memory array is nearly full.
Claim 24
Dependent Claim
29 words
The programmable integrated circuit of claim 14 wherein said memory array is configurable with respect to a width of said memory array and a depth of said memory array.
Claim 25
Dependent Claim
17 words
The programmable integrated circuit of claim 14 wherein said memory array is operated as a synchronous memory.
Claim 26
Dependent Claim
17 words
The programmable integrated circuit of claim 14 wherein said memory array is operated as an asynchronous memory.
Claim 27
Dependent Claim
13 words
A digital system having a programmable integrated circuit as recited in claim 14.
Claim 28
Dependent Claim
177 words
A programmable integrated circuit comprising: an interconnect grid; a first array block, programmably coupled to said interconnect grid; a second array block, programmably coupled to said interconnect grid, is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode, said second array block comprising: a memory array, said memory array having a plurality of memory cells arranged in a random access memory format and address lines to address said memory array; a first register coupled to said address lines of said memory array, said first register containing a write address when said second array block is in said FIFO mode; a second register coupled to said address lines of said memory array, said second register containing a read address when said second array block is in said FIFO mode; and a local interconnect, said local interconnect being programmably coupled to said interconnect grid, first register, and second register, wherein said first register and said second register are coupled to said address lines of said memory array without passing through said local interconnect.
Claim 29
Dependent Claim
177 words
A programmable integrated circuit comprising: an interconnect grid; a first array block, programmably coupled to said interconnect grid; a second array block, programmably coupled to said interconnect grid, is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode, said second array block comprising: a memory array, said memory array having a plurality of memory cells arranged in a random access memory format and address lines to address said memory array; a first register coupled to said address lines of said memory array, said first register containing a write address when said second array block is in said FIFO mode; a second register coupled to said address lines of said memory array, said second register containing a read address when said second array block is in said FIFO mode; and a local interconnect, said local interconnect being programmably coupled to said interconnect grid, first register, and second register, wherein said first register and said second register are coupled to said address lines of said memory array without passing through said local interconnect.
Claim 30
Dependent Claim
29 words
The programmable integrated circuit of claim 26 wherein when said second array block is in said FIFO mode, said first register and said second register are configured as counters.
Claim 31
Dependent Claim
64 words
The programmable integrated circuit of claim 26 wherein said address lines of said memory array further comprise: write address lines, said write address lines being coupled to said first register when said second array block is in said FIFO mode; and read address lines, said read address lines being coupled to said second register when said second array block is in said FIFO mode.
Claim 32
Dependent Claim
68 words
The programmable integrated circuit of claim 28 wherein said memory further comprises: a data-in port for storing data to a write address of said FIFO specified in said write address lines; and a data-out port for reading data from a read address of said FIFO specified in said read address lines, wherein data is readable on said data-out port concurrently with data being stored on said data-in port.
Claim 33
Dependent Claim
224 words
A programmable integrated circuit comprising: an interconnect grid comprising a plurality of horizontal conductors and a plurality of vertical conductors, wherein said vertical conductors may be programmably coupled to said horizontal conductors; a plurality of logic array blocks programmably coupled to said interconnect grid; and an embedded array block, programmably coupled to said interconnect grid wherein said embedded array block is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode and said embedded array block comprises: a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address said memory array; a first register coupled to said address lines of said memory array, wherein said first register stores a write address when said embedded array block is in said FIFO mode; a second register coupled to said address lines of said memory array, wherein said second register stores a read address when said embedded array block is in said FIFO mode; and a local interconnect, wherein said local interconnect is programmably coupled to said interconnect grid, first register, and second register, wherein one of said plurality of logic array blocks is configured to duplicate said first register and said second register, and to provide a status flag representative of a status of said memory array.
Claim 34
Dependent Claim
224 words
A programmable integrated circuit comprising: an interconnect grid comprising a plurality of horizontal conductors and a plurality of vertical conductors, wherein said vertical conductors may be programmably coupled to said horizontal conductors; a plurality of logic array blocks programmably coupled to said interconnect grid; and an embedded array block, programmably coupled to said interconnect grid wherein said embedded array block is configurable as a RAM in a RAM mode and a FIFO in a FIFO mode and said embedded array block comprises: a memory array, wherein said memory array comprises a plurality of memory cells arranged in a random access memory format and address lines to address said memory array; a first register coupled to said address lines of said memory array, wherein said first register stores a write address when said embedded array block is in said FIFO mode; a second register coupled to said address lines of said memory array, wherein said second register stores a read address when said embedded array block is in said FIFO mode; and a local interconnect, wherein said local interconnect is programmably coupled to said interconnect grid, first register, and second register, wherein one of said plurality of logic array blocks is configured to duplicate said first register and said second register, and to provide a status flag representative of a status of said memory array.
Claim 35
Dependent Claim
27 words
The programmable integrated circuit of claim 30 wherein when said embedded array block is in said RAM mode, said first register is configured as a D-type register.
Claim 36
Dependent Claim
63 words
The programmable integrated circuit of claim 30 wherein address lines of said memory array further comprise: write address lines, said write address lines being coupled to said first register when said embedded array block is in said FIFO mode; and read address lines, said read address lines being coupled to said second register when said embedded array block is in said FIFO mode.
Claim 37
Dependent Claim
54 words
The programmable integrated circuit of claim 30 further comprising: an address input multiplexer, wherein while said embedded array block is in said FIFO mode, said address input multiplexer selectively couples said address lines of said memory array to said first register during a write phase and to said second register during a read phase.
Claim 38
Dependent Claim
68 words
The programmable integrated circuit of claim 32 wherein said memory further comprises: a data-in port for storing data to a write address of said FIFO specified in said write address lines; and a data-out port for reading data from a read address of said FIFO specified in said read address lines, wherein data is readable on said data-out port concurrently with data being stored on said data-in port.
Claim 39
Dependent Claim
20 words
The programmable integrated circuit of claim 30 wherein said status flag is asserted when said memory array is nearly full.
Claim 40
Dependent Claim
29 words
The programmable integrated circuit of claim 30 wherein said memory array is configurable with respect to a width of said memory array and a depth of said memory array.
Claim 41
Dependent Claim
17 words
The programmable integrated circuit of claim 30 wherein said memory array is operated as a synchronous memory.
Claim 42
Dependent Claim
17 words
The programmable integrated circuit of claim 30 wherein said memory array is operated as an asynchronous memory.
Claim 43
Dependent Claim
13 words
A digital system having a programmable integrated circuit as recited in claim 30.
Claim 44
Dependent Claim
156 words
A programmable logic integrated circuit comprising: a programmable interconnect array; a plurality of configurable logic blocks programmably coupled to the programmable interconnect array; and a plurality of configurable memory blocks, programmably coupled to the programmable interconnect array, wherein a configurable memory block is operable as a random access memory in a RAM mode and a first-in, first-out memory in a FIFO mode and comprises: a local interconnect; a memory array comprising a read address input and write address input; a first register coupled to the local interconnect, wherein in the FIFO mode, the first register stores a write address and is coupled to the read address input of the memory array without passing through the local interconnect; and a second register coupled to the local interconnect, wherein in the FIFO mode, the second register stores a read address and is coupled to the write address input of the memory array without passing through the local interconnect.
Claim 45
Dependent Claim
156 words
A programmable logic integrated circuit comprising: a programmable interconnect array; a plurality of configurable logic blocks programmably coupled to the programmable interconnect array; and a plurality of configurable memory blocks, programmably coupled to the programmable interconnect array, wherein a configurable memory block is operable as a random access memory in a RAM mode and a first-in, first-out memory in a FIFO mode and comprises: a local interconnect; a memory array comprising a read address input and write address input; a first register coupled to the local interconnect, wherein in the FIFO mode, the first register stores a write address and is coupled to the read address input of the memory array without passing through the local interconnect; and a second register coupled to the local interconnect, wherein in the FIFO mode, the second register stores a read address and is coupled to the write address input of the memory array without passing through the local interconnect.
Claim 46
Dependent Claim
50 words
The programmable logic integrated circuit of claim 40 wherein a configurable memory block further comprises: a first multiplelxer coupled between the first register and the read address input of the memory array; and a second multiplexer coupled between the second register and the write address input of the memory array.
Claim 47
Dependent Claim
62 words
The programmable logic integrated circuit of claim 41 wherein a configurable memory block further comprises: a third register coupled to the local interconnect; a third multiplexer selectively coupling the third register or the local interconnect to the first and second multiplexers, wherein in the RAM mode, the third multiplexer is coupled to the read and write address inputs of the memory array.
Claim 48
Dependent Claim
16 words
The programmable logic integrated circuit of claim 40 wherein the first and second registers are counters.
Claim 49
Dependent Claim
16 words
The programmable logic integrated circuit of claim 40 wherein the memory array is a dual-port memory.
Claim 50
Dependent Claim
16 words
The programmable logic integrated circuit of claim 40 wherein the memory array is a synchronous memory.
Claim 51
Dependent Claim
16 words
The programmable logic integrated circuit of claim 40 wherein the memory array is an asynchronous memory.
Claim 52
Dependent Claim
37 words
The programmable logic integrated circuit of claim 40 wherein the memory array may be organized as 256 rows of 8 bits, 512 rows of 4 bits, 1024 rows of 2 bits, or 2048 rows of 1 bit.
Claim 53
Dependent Claim
23 words
The programmable logic integrated circuit of claim 43 wherein increment inputs to the first and second registers are coupled to the local interconnect.
Claim 54
Dependent Claim
16 words
The programmable logic integrated circuit of claim 40 wherein the memory array comprises SRAM memory cells.
Claim 55
Dependent Claim
21 words
The programmable logic integrated circuit of claim 42 wherein clock inputs to the first, second, and third registers are coupled together.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-01 | 2003-05-03 | 2003-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-01 | 2007-05-03 | 2007-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-01 | 2011-05-03 | 2011-11-02 | $7700.00 | Window Closed / Lapsed |