US5338982A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable logic device
Assignee: Kawasaki Microelectronics Inc
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Filing: 1992-03-26
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Granted: 1994-08-16
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Expires: 2012-03-26
Abstract
Abstract A semiconductor integrated circuit capable of electrically writing functions according to this invention comprises a plurality of logical blocks capable of electrically writing functions and wire elements capable of programmably connecting the logical blocks to each other. Each of the logical blocks includes a gate element as an output buffer having a control terminal. The gate element assumes a high impedance state when inputting a control signal to the control terminal. An output of the logical block is thereby made unable; or the respective logical blocks are directly wired-connectable to effect logical sum outputting. Alternatively, the gate element assumes two output states of an open drain output and a totem-pole output. Hence, in the semiconductor integrated circuit of this invention, it is possible to improve a gate using efficiency of the small-sized programmable logical blocks and attain a high-density and high-integrated programmable logic device.
Inventors
- 👤 Keiichi Kawana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
91 words
A semiconductor integrated circuit having electrically writable functions, comprising: a plurality of logical blocks having electrically writable functions; and wire elements capable of programmably connecting said logical blocks to each other, wherein each of said logical blocks includes a gate element having a control terminal connectable to output terminals of a plurality of other logical blocks, and said gate element is brought into a high impedance state when a signal assuming a predetermined level is inputted to said control terminal of said gate element to disable output of said logical block.
Claim 2
Dependent Claim
91 words
A semiconductor integrated circuit having electrically writable functions, comprising: a plurality of logical blocks having electrically writable functions; and wire elements capable of programmably connecting said logical blocks to each other, wherein each of said logical blocks includes a gate element having a control terminal connectable to output terminals of a plurality of other logical blocks, and said gate element is brought into a high impedance state when a signal assuming a predetermined level is inputted to said control terminal of said gate element to disable output of said logical block.
Claim 3
Dependent Claim
18 words
The semiconductor integrated circuit according to claim 1, wherein said gate element is a tri-state output gate element.
Claim 4
Dependent Claim
22 words
The semiconductor integrated circuit according to claim 1, wherein a logic of said control terminal of the gate element can be inverted.
Claim 5
Dependent Claim
98 words
A semiconductor integrated circuit having electrically writable functions, comprising: a plurality of logical blocks having electrically writable functions; and wire elements capable of programmably connecting said logical blocks to each other, wherein each of said logical blocks includes a programmable gate element having a control terminal, an output of said programmable gate element of said logical block is connectable to one of the control terminal and the output of an other of said programmable gate elements, and said programmable gate element assumes a first state of a totem-pole output and a second state of an open drain output.
Claim 6
Dependent Claim
98 words
A semiconductor integrated circuit having electrically writable functions, comprising: a plurality of logical blocks having electrically writable functions; and wire elements capable of programmably connecting said logical blocks to each other, wherein each of said logical blocks includes a programmable gate element having a control terminal, an output of said programmable gate element of said logical block is connectable to one of the control terminal and the output of an other of said programmable gate elements, and said programmable gate element assumes a first state of a totem-pole output and a second state of an open drain output.
Claim 7
Dependent Claim
29 words
The semiconductor integrated circuit according to claim 4, wherein an output terminal of said logical block is programmably connectable to one of power source terminals via a resistor element.
Claim 8
Dependent Claim
23 words
The semiconductor integrated circuit according to claim 4, wherein a logic of said control terminal of the programmable gate element can be inverted.
References Cited (Backward Citations)
US4223277A
Cited
US4758746A
Cited
US4833349A
Cited
US4847612A
Cited
US4987326A
Cited
US5185706A
Cited
US5028821A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-15 | 1998-02-14 | 1998-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-15 | 2002-02-14 | 2002-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-15 | 2006-02-14 | 2006-08-16 | $7700.00 | Window Closed / Lapsed |