Patent US5964893A successfully refreshed from Google Patents.
US5964893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system for performing a trace function and method therefor
Assignee: NXP USA Inc
•
Filing: 1995-08-30
•
Granted: 1999-10-12
•
Expires: 2015-08-30
Abstract
Abstract A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.
Inventors
- 👤 Joseph C. Circello
- 👤 Klaus R. Riedel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:49
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F17/00; G06F11/3648; G06F9/00
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
121 words
A data processor comprising: a central processor unit (CPU) for executing instructions, the instructions including a program counter relative branch instruction and variant branch instructions; a debug unit having an input coupled to the CPU, and a debug status output for providing a CPU status output portion and a data output portion, wherein: the debug unit for providing an active signal on the CPU status output portion and an inactive signal on the data output portion in response to the CPU executing the program counter relative branch instruction; and the debug unit for providing an active signal on the CPU status output portion and an active signal on the data output portion in response to the CPU executing variant branch instruction.
Claim 2
Dependent Claim
121 words
A data processor comprising: a central processor unit (CPU) for executing instructions, the instructions including a program counter relative branch instruction and variant branch instructions; a debug unit having an input coupled to the CPU, and a debug status output for providing a CPU status output portion and a data output portion, wherein: the debug unit for providing an active signal on the CPU status output portion and an inactive signal on the data output portion in response to the CPU executing the program counter relative branch instruction; and the debug unit for providing an active signal on the CPU status output portion and an active signal on the data output portion in response to the CPU executing variant branch instruction.
Claim 3
Dependent Claim
19 words
The data processor of claim 1, wherein the CPU status output portion is updated at least once per instruction.
Claim 4
Dependent Claim
27 words
The data processor of claim 1, wherein the CPU status output portion is for indicating at least a beginning of execution of at least one current instruction.
Claim 5
Dependent Claim
118 words
The data processor of claim 3, wherein the data processor further comprises: the instructions including a memory access instruction, wherein when the memory access instruction is executed there is a data operand having a maximum number of bits is transferred over the first bus; the data output portion of the external status port for displaying Y bits of data at once, wherein Y is less than the maximum number of bits; and the debug unit having a memory means for storing the data operand, and for controlling a display of the data operand over the data portion, wherein the debug unit sequentially displays the data operand Y bits at a time until the data operand has been displayed.
Claim 6
Dependent Claim
12 words
The data processor of claim 4, wherein Y is equal to 4.
Claim 7
Dependent Claim
19 words
The data processor of claim 5, where the maximum number of bits is greater than or equal to 16.
Claim 8
Dependent Claim
47 words
The data processor of claim 4, wherein the debug unit is for asserting on the CPU status output portion of the external status port an indicator that a new instruction is beginning, and an indicator of a number of bits of the data operand to be displayed.
Claim 9
Dependent Claim
32 words
The data processor of claim 1, wherein the data processor includes a control register having a control bit, wherein the data output portion is enabled only when the control bit is active.
Claim 10
Dependent Claim
76 words
The data processor of claim 1, wherein the data processor further comprises: the CPU for executing a branch instruction wherein, when a branch is taken, there is a destination address; a memory location coupled to the debug unit for specifying whether a portion of the destination address is to be displayed on the data portion; and the debug unit for displaying the portion of the destination address specified in the memory location on the data portion.
Claim 11
Dependent Claim
65 words
The data processor of claim 1, wherein the data processor further comprises: the debug unit is for providing ant first active signal on the CPU status output portion at a first time and a second active signal on the data output portion at a second time, wherein a difference between a beginning of the first time and a beginning of the second time is deterministic.
Claim 12
Dependent Claim
16 words
The data processor of claim 10, wherein the second time is a predetermined amount of time.
Claim 13
Dependent Claim
16 words
The data processor of claim 10, wherein the second time is synchronous to the first time.
Claim 14
Dependent Claim
51 words
The data processor of claim 1, wherein the CPU is for providing an instruction status and the data output portion is for providing one of an operand and a branch address wherein the branch address is provide at a predetermined number of clock cycles relative to the instruction status being asserted.
Claim 15
Independent Claim
126 words
A method of monitoring a data processor, the method comprising: defining a set of status codes, wherein the set of status codes comprises: 1) a status code indicating a beginning of execution of a branch taken instruction; 2) a status code indicating a beginning of a return from exception; 3) a status code indicating a beginning execution of a pulse instruction; or 4) a status code indicating a beginning execution for other instructions; and receiving a first instruction from a first bus; beginning a normal mode of execution of the first instruction using a central processor unit (CPU); displaying external to the data processor on the first status code, wherein the first status code is selected from the set of status codes depending the first instruction.
Claim 16
Independent Claim
126 words
A method of monitoring a data processor, the method comprising: defining a set of status codes, wherein the set of status codes comprises: 1) a status code indicating a beginning of execution of a branch taken instruction; 2) a status code indicating a beginning of a return from exception; 3) a status code indicating a beginning execution of a pulse instruction; or 4) a status code indicating a beginning execution for other instructions; and receiving a first instruction from a first bus; beginning a normal mode of execution of the first instruction using a central processor unit (CPU); displaying external to the data processor on the first status code, wherein the first status code is selected from the set of status codes depending the first instruction.
Claim 17
Independent Claim
156 words
A method of monitoring a data processor, the method comprising: receiving a first instruction from a first bus; beginning execution of the first instruction, using a central processor unit (CPU), wherein there is data associated with the first instruction; sending an internal status code on a second bus from the CPU to a debug portion of the data processor when the CPU begins execution of the first instruction; capturing the data for use by the debug portion; displaying on a first portion of an external status port, via the debug portion of the data processor, a representation of the internal status code; displaying on the first portion of the external status port, a data transfer status indicating that the data is to be transferred over a debug data port; and displaying at least a portion of the data on the debug data port at a predetermined amount of time after the displaying the data transfer status.
Claim 18
Independent Claim
156 words
A method of monitoring a data processor, the method comprising: receiving a first instruction from a first bus; beginning execution of the first instruction, using a central processor unit (CPU), wherein there is data associated with the first instruction; sending an internal status code on a second bus from the CPU to a debug portion of the data processor when the CPU begins execution of the first instruction; capturing the data for use by the debug portion; displaying on a first portion of an external status port, via the debug portion of the data processor, a representation of the internal status code; displaying on the first portion of the external status port, a data transfer status indicating that the data is to be transferred over a debug data port; and displaying at least a portion of the data on the debug data port at a predetermined amount of time after the displaying the data transfer status.
References Cited (Backward Citations)
US3937938A
Cited
US4080650A
Cited
US4338660A
Cited
US4675646A
Cited
US4635193A
Cited
US5165027A
Cited
EP0271910A2
Cited
GB2200482A
Cited
US5132971A
Cited
US4819234A
Cited
US5179696A
Cited
US5084814A
Cited
US5053949A
Cited
US5157781A
Cited
US5361348A
Cited
US5313608A
Cited
US5301198A
Cited
US5410685A
Cited
US5204864A
Cited
US5291497A
Cited
US5341500A
Cited
US5371894A
Cited
US5517659A
Cited
US5321828A
Cited
US5357628A
Cited
US5479652B1
Cited
US5479652A
Cited
US5491793A
Cited
US5367550A
Cited
US5379301A
Cited
US5359608A
Cited
US5455936A
Cited
EP0636976A1
Cited
US5488688A
Cited
US5530804A
Cited
US5623673A
Cited
US5630102A
Cited
US5546562A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-11 | 2003-04-12 | 2003-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-11 | 2007-04-12 | 2007-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-11 | 2011-04-12 | 2011-10-12 | $7700.00 | Window Closed / Lapsed |