Microprocessor with cache memory for supporting debugging operations

Claim 2

A microprocessor for supporting debugging operations while executing arithmetic processing by utilizing pieces of data stored in an external memory, said microprocessor comprising: arithmetic-logic means for executing arithmetic processing by utilizing said pieces of data; and debugging supporting means comprising a holding section for holding a designated address AD1, and a detecting section for detecting an address signal indicating said designated address AD1 held in said holding section from among address signals provided from said arithmetic-logic means to an external address bus; said arithmetic-logic means being located separately from said debugging supporting means and comprising a cache memory for storing each piece of said data at an address, a tag memory for storing addresses existing in said cache memory, an arithmetic unit for reading out a piece of data stored in said cache memory and executing arithmetic processing utilizing said piece of data, a control section for sending an address checking signal to said tag memory to check whether or not an address AD2 is stored in said tag memory when a piece of data stored at said address AD2 of said cache memory is required by said arithmetic unit, providing a group of address signals which indicates a group of addresses AD including said address AD2 to said external address bus to fetch pieces of data DA stored at addresses AD of said external memory in cases where said address AD2 is not stored in said tag memory, providing said addresses AD to said tag memory, and providing said pieces of data DA stored in said external memory to said cache memory, a tagging section for tagging said designated address AD1 with a designating signal stored in said tag memory under control of said control section when the said address signal indicating said designated address AD1 is detected by said detecting section of said debugging supporting means, and a command signal generating section for generating a command signal when said designated address AD1 tagged by said tagging section is accessed by said address checking signal sent by said control section, and for providing said common signal to said control section to brake said arithmetic processing executed in said arithmetic unit, wherein said arithmetic processing executed in said arithmetic unit is braked under control of said control section after said command signal is provided to said control section.

Claim 3

A microprocessor according to claim 1 in which said command signal generated by said command signal generating section is an annunciation signal which annunciates that a piece of data DA1 stored at said designated address AD1 is accessed and read out to said arithmetic unit from the said cache memory.

Claim 4

A microprocessor according to claim 1 in which said command signal generated by said command signal generating section is a brake signal which forcibly halts arithmetic processing executed in said arithmetic unit under control of said control section.

Claim 5

A microprocessor according to claim 1 in which said designated address AD1 is tagged with a binary digit in said tagging section.

Claim 6

A microprocessor with a cache memory for supporting debugging operations while executing arithmetic processing by utilizing pieces of data stored in an external memory, said microprocessor comprising: arithmetic-logic means for executing arithmetic processing by utilizing said pieces of data; and debugging supporting means comprising a holding section for holding designated data DA1; a detecting section for detecting a piece of data agreeing with said designated data DA1 held in said holding section from among a group of pieces of data provided from said external memory to an external data bus; said arithmetic-logic means being located separately from said debugging supporting means and comprising said cache memory for storing each piece of said data at an address, a tag memory for storing addresses existing in said cache memory, an arithmetic unit for reading out a piece of data stored in said cache memory and executing arithmetic processing utilizing said piece of data, a control section for sending an address checking signal to said tag memory to check whether or not an address AD2 is stored in said tag memory when a piece of data DA2 stored at said address AD2 of said cache memory is required by said arithmetic unit, providing a group of address signals which indicates a group of addresses AD including said address AD2 to an external address bus to fetch pieces of data DA including data DA2 stored at said addresses AD of said external memory through said external data bus in cases where said address AD2 is not stored in said tag memory, providing said addresses AD to said tag memory, and providing said pieces of data DA stored in said external memory to said cache memory, a tagging section for tagging said address AD1 with a designating signal stored in said tag memory under control of said control section when data agreeing with said designated data DA held in said holding section is detected by said detecting section of said debugging supporting means and a command signal generating section for generating a command signal when said address AD1 tagged by said tagging section is accessed by said address sent by said control section, and providing said command signal to said control section to brake arithmetic processing executed in said arithmetic unit, wherein said arithmetic processing executed in said arithmetic unit is braked under control of said control section after said command signal is provided to said control section.

Claim 7

A microprocessor with a cache memory for supporting debugging operations while executing arithmetic processing by utilizing pieces of data stored in an external memory, said microprocessor comprising: arithmetic-logic means for executing arithmetic processing by utilizing said pieces of data; and debugging supporting means comprising a holding section for holding designated data DA1; a detecting section for detecting a piece of data agreeing with said designated data DA1 held in said holding section from among a group of pieces of data provided from said external memory to an external data bus; said arithmetic-logic means being located separately from said debugging supporting means and comprising said cache memory for storing each piece of said data at an address, a tag memory for storing addresses existing in said cache memory, an arithmetic unit for reading out a piece of data stored in said cache memory and executing arithmetic processing utilizing said piece of data, a control section for sending an address checking signal to said tag memory to check whether or not an address AD2 is stored in said tag memory when a piece of data DA2 stored at said address AD2 of said cache memory is required by said arithmetic unit, providing a group of address signals which indicates a group of addresses AD including said address AD2 to an external address bus to fetch pieces of data DA including data DA2 stored at said addresses AD of said external memory through said external data bus in cases where said address AD2 is not stored in said tag memory, providing said addresses AD to said tag memory, and providing said pieces of data DA stored in said external memory to said cache memory, a tagging section for tagging said address AD1 with a designating signal stored in said tag memory under control of said control section when data agreeing with said designated data DA held in said holding section is detected by said detecting section of said debugging supporting means and a command signal generating section for generating a command signal when said address AD1 tagged by said tagging section is accessed by said address sent by said control section, and providing said command signal to said control section to brake arithmetic processing executed in said arithmetic unit, wherein said arithmetic processing executed in said arithmetic unit is braked under control of said control section after said command signal is provided to said control section.

Claim 8

A microprocessor according to claim 5 in which said command signal generated by said command signal generating section is a brake signal which forcibly halts arithmetic processing executed in said arithmetic unit under control of said control section.

Claim 9

A microprocessor according to claim 5 in which said command signal generated by said command signal generating section is an annunciating signal which annunciates that said designated data DA1 is accessed and read out to said arithmetic unit from said cache memory.

Claim 10

A microprocessor according to claim 5 in which said designated address AD1 is tagged with a binary digit in said tagging section.