Method of making NMOS and PMOS devices having LDD structures using separate drive-in steps

Claim 3

The method of claim 1, including: driving-in the first dopant at a first temperature; and driving-in the second dopant at a second temperature, wherein the first temperature is substantially greater than the second temperature.

Claim 4

The method of claim 2, wherein the first temperature exceeds the second temperature by at least 50° C.

Claim 5

The method of claim 2, wherein at the second temperature the second dopant diffuses into the substrate at a substantially greater rate than the first dopant.

Claim 6

The method of claim 2, wherein the first dopant is selected from the group consisting of arsenic, phosphorus, and combinations thereof, and the second dopant is selected from the group consisting of boron, boron species and combinations thereof.

Claim 7

The method of claim 1 wherein the N-channel and P-channel devices provide a CMOS inverter circuit.

Claim 8

The method of claim 1, wherein introducing the first dopant includes: implanting a light dose of an N-type dopant into portions of the first active region to provide lightly doped source and drain regions that are aligned with opposing sidewalls of a first gate; and then implanting a heavy dose of an N-type dopant into portions of the first active region to provide heavily doped source and drain regions that are aligned with first spacers formed adjacent to the opposing sidewalls of the first gate.

Claim 9

The method of claim 1, wherein introducing the second dopant includes: implanting a light dose of a P-type dopant into portions of the second active region to provide lightly doped source and drain regions that are aligned with opposing sidewalls of the second gate; and then implanting a heavy dose of a P-type dopant into portions of the second active region to provide heavily doped source and drain regions that are aligned with second spacers formed adjacent to the opposing sidewalls of the second gate.

Claim 10

The method of claim 1, wherein: introducing the first dopant includes implanting a light dose of an N-type dopant into portions of the first active region to provide lightly doped source and drain regions that are aligned with opposing sidewalls of the first gate, and implanting a heavy dose of an N-type dopant into portions of the first active region to provide heavily doped source and drain regions that are aligned with first spacers formed adjacent to the opposing sidewalls of the first gate; driving-in the first dopant merges the lightly doped and heavily doped source and drain regions in the first active region to form the source and the drain in the first active region; introducing the second dopant includes implanting a light dose of a P-type dopant into portions of the second active region to provide lightly doped source and drain regions that are aligned with opposing sidewalls of the second gate, and implanting a heavy dose of a P-type dopant into portions of the second active region to provide heavily doped source and drain regions that are aligned with second spacers formed adjacent to the opposing sidewalls of the second gate; and driving-in the second dopant merges the lightly doped and heavily doped source and drain regions in the second active region to form the source and the drain in the second active region.

Claim 13

The method of claim 10, wherein: the N-channel device is formed in the first active region; the P-channel device is formed in the second active region; the dopant of first conductivity type is selected from the group consisting of arsenic, phosphorus, and combinations thereof; and the dopant of second conductivity type is selected from the group consisting of boron, boron species and combinations thereof.

Claim 14

The method of claim 10, wherein: introducing the dopant of second conductivity type includes implanting a light dose of an N-type dopant into the first active region and then implanting a heavy dose of an N-type dopant into the first active region; and introducing the dopant of first conductivity type includes implanting a light dose of a P-type dopant into the second active region and then implanting a heavy dose of a P-type dopant into the second active region.

Claim 15

The method of claim 10, wherein the first and second temperatures are in the range of about 950 to 1050° C.

Claim 16

The method of claim 10, wherein: driving-in the dopant of second conductivity type includes applying a first rapid thermal anneal; and driving-in the dopant of second conductivity type includes applying a second rapid thermal anneal.

Claim 19

The method of claim 15, wherein the N-type dopant is selected from the group consisting of arsenic, phosphorus, and combinations thereof, and the P-type dopant is selected from the group consisting of boron, boron species and combinations thereof.

Claim 20

The method of claim 15, wherein the first and second temperatures are in the range of about 950 to 1050° C.

Claim 21

The method of claim 15, including simultaneously etching the first and second portions of the polysilicon layer.

Claim 22

The method of claim 15, including sequentially etching the first and second portions of the polysilicon layer.

Claim 23

The method of claim 18, including simultaneously forming first spacers adjacent to opposing sidewalls of the first gate and second spacers adjacent to opposing sidewalls of the second gate.

Claim 24

The method of claim 19, including forming first spacers adjacent to opposing sidewalls of the first gate and then forming second spacers adjacent to opposing sidewalls of the second gate.

Claim 25

The method of claim 15, wherein: implanting the N-type dopant includes implanting a light dose of a first N-type dopant into the NMOS region outside the first gate and then implanting a heavy dose of a second N-type dopant into the NMOS region outside the first gate and first spacers adjacent to opposing sidewalls of the first gate; and implanting the P-type dopant includes implanting a light dose of a first P-type dopant into the PMOS region outside the second gate and then implanting a heavy dose of a second P-type dopant into the PMOS region outside the second gate and second spacers adjacent to opposing sidewalls of the second gate.

Claim 26

The method of claim 15, including the following steps in the sequence set forth: forming a first photoresist layer over the substrate with an opening that selectively exposes the first portion of the polysilicon layer; etching the first portion of the polysilicon layer through the opening in the first photoresist layer to form the first gate; implanting a light dose of a first N-type dopant through the opening in the first photoresist layer into the NMOS region outside the first gate to provide lightly doped source and drain regions in the NMOS region; stripping the first photoresist layer; forming first spacers adjacent to opposing sidewalls of the first gate; forming a second photoresist layer over the substrate with an opening that selectively exposes the NMOS region; implanting a heavy dose of a second N-type dopant through the opening in the second photoresist layer into the NMOS region outside the first gate and the first spacers to provide heavily doped source and drain regions in the NMOS region; stripping the second photoresist layer; driving-in the first and second N-type dopants so that the lightly doped and heavily doped source regions in the NMOS region provide the N-type source, and the lightly doped and heavily doped drain regions in the NMOS region provide the N-type drain; forming a third photoresist layer over the substrate with an opening that selectively exposes the second portion of the polysilicon layer; etching the second portion of the polysilicon layer through the opening in the third photoresist layer to form the second gate; implanting a light dose of a first P-type dopant through the opening in the third photoresist layer into the PMOS region outside the second gate to provide lightly doped source and drain regions in the PMOS region; stripping the third photoresist layer; forming second spacers adjacent to opposing sidewalls of the second gate; forming a fourth photoresist layer over the substrate with an opening that selectively exposes the PMOS region; implanting a heavy dose of a second P-type dopant through the opening in the fourth photoresist layer into the PMOS region outside the second gate and the second spacers to provide heavily doped source and drain regions in the PMOS region; stripping the fourth photoresist layer; and driving-in the first and second P-type dopants so that the lightly doped and heavily doped source regions in the PMOS region provide the P-type source, and the lightly doped and heavily doped drain regions in the PMOS region provide the P-type drain.

Claim 27

The method of claim 15, including the following steps in the sequence set forth: simultaneously etching the first and second portions of the polysilicon layer to simultaneously form the first and second gates; forming a first photoresist layer over the substrate with an opening that selectively exposes the NMOS region; implanting a light dose of a first N-type dopant through the opening in the first photoresist layer into the NMOS region outside the first gate to provide lightly doped source and drain regions in the NMOS region; stripping the first photoresist layer; forming first spacers adjacent to opposing sidewalls of the first gate and second spacers adjacent to opposing sidewalls of the second gate; forming a second photoresist layer over the substrate with an opening that selectively exposes the NMOS region; implanting a heavy dose of a second N-type dopant through the opening in the second photoresist layer into the NMOS region outside the first gate and the first spacers to provide heavily doped source and drain regions in the NMOS region; stripping the second photoresist layer; driving-in the first and second N-type dopants so that the lightly doped and heavily doped source regions in the NMOS region provide the N-type source, and the lightly doped and heavily doped drain regions in the NMOS region provide the N-type drain; forming a third photoresist layer over the substrate with an opening that selectively exposes the PMOS region; implanting a heavy dose of a first P-type dopant through the opening in the third photoresist layer into the PMOS region outside the second gate and the second spacers to provide heavily doped source and drain regions in the PMOS region; stripping the third photoresist layer; removing the second spacers; forming a fourth photoresist layer over the substrate with an opening that selectively exposes the PMOS region; implanting a light dose of a second P-type dopant into the PMOS region outside the second gate to provide lightly doped source and drain regions in the PMOS region; stripping the fourth photoresist layer; and driving-in the first and second P-type dopants so that the lightly doped and heavily doped source regions in the PMOS region provide the P-type source, and the lightly doped and heavily doped drain regions in the PMOS region provide the P-type drain.