Method of fabricating field effect transistors having lightly doped drain regions

Claim 1

A method of fabricating a field effect transistor having a lightly doped drain region, comprising the sequential steps of: (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a nitride layer over said substrate including said gate; (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions into said substrate and about the side edges of said gate using said oxide sidewall spacers as masks; and (g) implanting the lightly doped drain region about one of the side edges of said gate adjacent to said heavily doped drain region.

Claim 2

A method of fabricating a field effect transistor having a lightly doped drain region, comprising the sequential steps of: (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a nitride layer over said substrate including said gate; (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions into said substrate and about the side edges of said gate using said oxide sidewall spacers as masks; and (g) implanting the lightly doped drain region about one of the side edges of said gate adjacent to said heavily doped drain region.

Claim 6

A method of fabricating a field effect transistor having a lightly doped drain region, comprising the sequential steps of: (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a nitride layer over said substrate including said gate; (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions into said substrate and about the side edges of said gate using said oxide sidewall spacers as masks; (g) removing said oxide sidewall spacers; and (h) implanting the lightly doped drain region about one of the side edges of said gate adjacent to said heavily doped drain region.

Claim 7

A method of fabricating a field effect transistor having a lightly doped drain region, comprising the sequential steps of: (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a nitride layer over said substrate including said gate; (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions into said substrate and about the side edges of said gate using said oxide sidewall spacers as masks; (g) removing said oxide sidewall spacers; and (h) implanting the lightly doped drain region about one of the side edges of said gate adjacent to said heavily doped drain region.

Claim 10

A method of fabricating a field effect transistor having a lightly doped drain region, comprising the sequential steps of: (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a nitride layer over said substrate including said gate; (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions of a conductivity type into said substrate and about the side edges of said gate using said oxide sidewall spacers as masks; (g) removing said oxide sidewall spacers; and (h) implanting the lightly doped drain region of said conductivity type about one of the side edges of said gate immediately adjacent to said heavily doped drain region.

Claim 11

A method of fabricating a field effect transistor having a lightly doped drain region, comprising the sequential steps of: (a) providing a substrate having an active region defined by field oxide regions; (b) providing a gate, having side edges, overlying a portion of said active region; (c) forming a nitride layer over said substrate including said gate; (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride layer to form oxide sidewall spacers about the side edges of said gate; (f) implanting heavily doped source and drain regions of a conductivity type into said substrate and about the side edges of said gate using said oxide sidewall spacers as masks; (g) removing said oxide sidewall spacers; and (h) implanting the lightly doped drain region of said conductivity type about one of the side edges of said gate immediately adjacent to said heavily doped drain region.

Claim 13

A method of fabricating a complementary MOS transistor having first and second lightly doped drain regions, comprising the sequential steps of: (a) providing a substrate having a first active region with a first conductivity type and a second active region with a second conductivity type defined by field oxide regions; (b) providing a first gate, having side edges, overlying a portion of said first active region, and a second gate, having side edges, overlying a portion of said second active region; (c) forming a nitride material layer over said substrate including said first and second gates; (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride material layer form oxide sidewall spacers about the side edges of said first and second gates; (f) forming a first disposable barrier material layer over selected areas of the substrate including said second active region and excluding said first active region using a first mask; (g) implanting first heavily doped source and drain regions of said second conductivity type into said substrate and about the side edges of said first gate using said oxide sidewall spacers as second masks while said second active area is protected by said first disposable barrier material layer; and (h) implanting the first lightly doped drain region of said second conductivity type about one of the side edges of said first gate adjacent to said first heavily doped drain region while said second active area is protected by said first disposable barrier material layer.

Claim 14

A method of fabricating a complementary MOS transistor having first and second lightly doped drain regions, comprising the sequential steps of: (a) providing a substrate having a first active region with a first conductivity type and a second active region with a second conductivity type defined by field oxide regions; (b) providing a first gate, having side edges, overlying a portion of said first active region, and a second gate, having side edges, overlying a portion of said second active region; (c) forming a nitride material layer over said substrate including said first and second gates; (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride material layer form oxide sidewall spacers about the side edges of said first and second gates; (f) forming a first disposable barrier material layer over selected areas of the substrate including said second active region and excluding said first active region using a first mask; (g) implanting first heavily doped source and drain regions of said second conductivity type into said substrate and about the side edges of said first gate using said oxide sidewall spacers as second masks while said second active area is protected by said first disposable barrier material layer; and (h) implanting the first lightly doped drain region of said second conductivity type about one of the side edges of said first gate adjacent to said first heavily doped drain region while said second active area is protected by said first disposable barrier material layer.

Claim 20

A method of fabricating a complementary MOS transistor having a first and a second lightly doped drain regions, comprising the sequential steps of: (a) providing a substrate having a first active region with a first conductivity type and a second active region with a second conductivity type defined by field oxide regions; (b) providing a first gate, having side edges, overlying a portion of said first active region, and a second gate, having side edges, overlying a portion of said second active region; (c) forming a first barrier material layer over said substrate including said first and second gates, wherein said first barrier material layer is composed of nitride; and (d) forming an oxide layer over said first barrier material layer; (e) selectively etching said oxide layer with respect to said first barrier material layer to form oxide sidewall spacers about the side edges of said first and second gates; (f) forming a second disposable barrier material layer over selected areas of the substrate including said second active region and excluding said first active region using a first mask; (g) implanting first heavily doped source and drain regions of said second conductivity type into said substrate and about the side edges of said first gate using said oxide sidewall spacers as second masks while said second active area is protected by said second disposable barrier material layer; (h) removing said oxide sidewall spacers along the side edges of said first gate; (i) implanting the first lightly doped drain region of said second conductivity type about one of the side edges of said first gate adjacent to said first heavily doped drain region while said second active area is protected by said second disposable barrier material layer; (j) forming a third disposable barrier material layer over selected areas of the substrate including said first active region and excluding said second active region using a third mask; (k) implanting second heavily doped source and drain regions of said first conductivity type into said substrate and about the side edges of said second gate using said oxide sidewall spacers as fourth masks while said first active area is protected by said third disposable barrier material layer; (l) removing said oxide sidewall spacers along the side edges of said second gate; and (m) implanting the second lightly doped drain region of said first conductivity type about one of the side edges of said second gate adjacent to said second heavily doped drain region while said first active area is protected by said second disposable barrier material layer.

Claim 21

A method of fabricating a complementary MOS transistor having a first and a second lightly doped drain regions, comprising the sequential steps of: (a) providing a substrate having a first active region with a first conductivity type and a second active region with a second conductivity type defined by field oxide regions; (b) providing a first gate, having side edges, overlying a portion of said first active region, and a second gate, having side edges, overlying a portion of said second active region; (c) forming a first barrier material layer over said substrate including said first and second gates, wherein said first barrier material layer is composed of nitride; and (d) forming an oxide layer over said first barrier material layer; (e) selectively etching said oxide layer with respect to said first barrier material layer to form oxide sidewall spacers about the side edges of said first and second gates; (f) forming a second disposable barrier material layer over selected areas of the substrate including said second active region and excluding said first active region using a first mask; (g) implanting first heavily doped source and drain regions of said second conductivity type into said substrate and about the side edges of said first gate using said oxide sidewall spacers as second masks while said second active area is protected by said second disposable barrier material layer; (h) removing said oxide sidewall spacers along the side edges of said first gate; (i) implanting the first lightly doped drain region of said second conductivity type about one of the side edges of said first gate adjacent to said first heavily doped drain region while said second active area is protected by said second disposable barrier material layer; (j) forming a third disposable barrier material layer over selected areas of the substrate including said first active region and excluding said second active region using a third mask; (k) implanting second heavily doped source and drain regions of said first conductivity type into said substrate and about the side edges of said second gate using said oxide sidewall spacers as fourth masks while said first active area is protected by said third disposable barrier material layer; (l) removing said oxide sidewall spacers along the side edges of said second gate; and (m) implanting the second lightly doped drain region of said first conductivity type about one of the side edges of said second gate adjacent to said second heavily doped drain region while said first active area is protected by said second disposable barrier material layer.

Claim 25

A method of fabricating a complementary MOS transistor having a lightly doped N conductivity region and a lightly doped P conductivity drain region, comprising the sequential steps of: (a) providing a substrate having a first active region with a P conductivity type and a second active region with a N conductivity type defined by field oxide regions; (b) providing a first gate, having side edges, overlying a portion of said first active region, and a second gate, having side edges, overlying a portion of said second active region; (c) forming a nitride layer over said substrate including said first and second gates; and (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride layer to form sidewall spacers about the side edges of said first and second gates; (f) forming a first photoresist material layer over selected areas of the substrate including said second active region and excluding said first active region using a first mask; (g) implanting first heavily doped source and drain regions of N conductivity type into said substate and about the side edges of said first gate using said oxide sidewall spacers as second masks while said second active area is protected by said first photoresist material layer; (h) removing said oxide sidewall spacers about the side edges of said first gate; (i) implanting the first lightly doped drain region of N conductivity type about one of the side edges of said first gate adjacent to said first heavily doped N conductivity type drain region while said second active area is protected by said first photoresist material layer; (j) forming a second photoresist material layer over selected areas of the substrate including said first active region and excluding said second active region using a third mask; (k) implanting heavily doped source and drain regions of P conductivity type into said substrate and about the side edges of said second gate using said oxide sidewall spacers as fourth masks while said first active area is protected by said second photoresist material layer; (l) removing said oxide sidewall spacers about the side edges of said second gate; and (m) implanting the second lightly doped drain region of P conductivity type about one of the side edges of said second gate adjacent to said heavily doped P conductivity type drain region while said first active area is protected by said second photoresist material layer.

Claim 26

A method of fabricating a complementary MOS transistor having a lightly doped N conductivity region and a lightly doped P conductivity drain region, comprising the sequential steps of: (a) providing a substrate having a first active region with a P conductivity type and a second active region with a N conductivity type defined by field oxide regions; (b) providing a first gate, having side edges, overlying a portion of said first active region, and a second gate, having side edges, overlying a portion of said second active region; (c) forming a nitride layer over said substrate including said first and second gates; and (d) forming an oxide layer over said nitride layer; (e) selectively etching said oxide layer with respect to said nitride layer to form sidewall spacers about the side edges of said first and second gates; (f) forming a first photoresist material layer over selected areas of the substrate including said second active region and excluding said first active region using a first mask; (g) implanting first heavily doped source and drain regions of N conductivity type into said substate and about the side edges of said first gate using said oxide sidewall spacers as second masks while said second active area is protected by said first photoresist material layer; (h) removing said oxide sidewall spacers about the side edges of said first gate; (i) implanting the first lightly doped drain region of N conductivity type about one of the side edges of said first gate adjacent to said first heavily doped N conductivity type drain region while said second active area is protected by said first photoresist material layer; (j) forming a second photoresist material layer over selected areas of the substrate including said first active region and excluding said second active region using a third mask; (k) implanting heavily doped source and drain regions of P conductivity type into said substrate and about the side edges of said second gate using said oxide sidewall spacers as fourth masks while said first active area is protected by said second photoresist material layer; (l) removing said oxide sidewall spacers about the side edges of said second gate; and (m) implanting the second lightly doped drain region of P conductivity type about one of the side edges of said second gate adjacent to said heavily doped P conductivity type drain region while said first active area is protected by said second photoresist material layer.