US5618748A
Expired / Lapsed
US
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Manufacturing method of CMOS transistor with no reduction of punch-through voltage
Assignee: Panasonic Holdings Corp
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Filing: 1995-05-17
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Granted: 1997-04-08
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Expires: 2015-05-17
Abstract
Abstract Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
Inventors
- 👤 Mizuki Segawa
- 👤 Yoshiaki Kato
- 👤 Hiroaki Nakaoka
- 👤 Takashi Nakabayashi
- 👤 Atsushi Hori
- 👤 Hiroshi Masuda
- 👤 Ichiro Matsuo
- 👤 Akihira Shinohara
- 👤 Takashi Uehara
- 👤 Mitsuo Yasuhira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:25
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/147
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
154 words
A method of manufacturing a CMOS transistor, said method comprising the steps of: forming gate electrodes of an N-channel transistor and a P-channel transistor on a semiconductor substrate with a gate insulating layer therebetween; forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using the gate electrode of the N-channel transistor as a mask; conducting a first thermal treatment to said gate electrodes and said N-type heavily doped diffusion layers at a first temperature; forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using the gate electrode of the P-channel transistor as a mask; and conducting a second thermal treatment to said P-type heavily doped diffusion layers at a second temperature lower than that of said first thermal treatment, a difference in temperature between said first temperature and said second temperature being a minimum of approximately 50° C.
Claim 2
Independent Claim
154 words
A method of manufacturing a CMOS transistor, said method comprising the steps of: forming gate electrodes of an N-channel transistor and a P-channel transistor on a semiconductor substrate with a gate insulating layer therebetween; forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using the gate electrode of the N-channel transistor as a mask; conducting a first thermal treatment to said gate electrodes and said N-type heavily doped diffusion layers at a first temperature; forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using the gate electrode of the P-channel transistor as a mask; and conducting a second thermal treatment to said P-type heavily doped diffusion layers at a second temperature lower than that of said first thermal treatment, a difference in temperature between said first temperature and said second temperature being a minimum of approximately 50° C.
Claim 3
Dependent Claim
47 words
The method of manufacturing a CMOS transistor according to claim 1, wherein said gate electrodes have a laminated structure composed of a polycrystalline silicon to which an N-type or P-type impurity is doped and a silicide of a high-melting-point metal which is laminated on the polycrystalline silicon.
References Cited (Backward Citations)
US4553315A
Cited
US4891326A
Cited
US4642878A
Cited
US4764477A
Cited
US4886764A
Cited
US4997782A
Cited
US4978626A
Cited
US5006477A
Cited
US5234850A
Cited
US5320975A
Cited
US5409847A
Cited
US5447872A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-04-07 | 2000-10-07 | 2001-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-04-07 | 2004-10-07 | 2005-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-04-07 | 2008-10-07 | 2009-04-08 | $7700.00 | Window Closed / Lapsed |