US5409847A
Expired / Lapsed
US
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Manufacturing method of CMOS transistor in which heat treatment at higher temperature is done prior to heat treatment at low temperature
Assignee: Panasonic Holdings Corp
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Filing: 1993-10-27
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Granted: 1995-04-25
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Expires: 2013-10-27
Abstract
Abstract Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
Inventors
- 👤 Mizuki Segawa
- 👤 Yoshiaki Kato
- 👤 Hiroaki Nakaoka
- 👤 Takashi Nakabayashi
- 👤 Atsushi Hori
- 👤 Hiroshi Masuda
- 👤 Ichiro Matsuo
- 👤 Akihira Shinohara
- 👤 Takashi Uehara
- 👤 Mitsuo Yasuhira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:59
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/147
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
227 words
A method of manufacturing a CMOS transistor, comprising the steps of: forming gate electrodes of an N-channel transistor and a P-channel transistor on a semiconductor substrate with a gate insulating layer therebetween; forming N-type lightly doped diffusion layers to be a source or a drain of the N-channel transistor, using the gate electrode of the N-channel transistor as a mask; conducting a first thermal treatment to said gate electrodes and said N-type lightly doped diffusion layers of the N-channel transistor; forming P-type lightly doped diffusion layers to be a source or a drain of the P-channel transistor, using the gate electrode of the P-channel transistor as a mask; forming side walls on side surfaces of said gate electrodes of the N-channel transistor and the P-channel transistor; forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode and said side walls of the N-channel transistor as a mask; forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using said gate electrode and said side walls of the P-channel transistor as a mask; and conducting a second thermal treatment to said P-type lightly doped diffusion layers, said N-type heavily doped diffusion layers and said P-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment.
Claim 2
Independent Claim
227 words
A method of manufacturing a CMOS transistor, comprising the steps of: forming gate electrodes of an N-channel transistor and a P-channel transistor on a semiconductor substrate with a gate insulating layer therebetween; forming N-type lightly doped diffusion layers to be a source or a drain of the N-channel transistor, using the gate electrode of the N-channel transistor as a mask; conducting a first thermal treatment to said gate electrodes and said N-type lightly doped diffusion layers of the N-channel transistor; forming P-type lightly doped diffusion layers to be a source or a drain of the P-channel transistor, using the gate electrode of the P-channel transistor as a mask; forming side walls on side surfaces of said gate electrodes of the N-channel transistor and the P-channel transistor; forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode and said side walls of the N-channel transistor as a mask; forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using said gate electrode and said side walls of the P-channel transistor as a mask; and conducting a second thermal treatment to said P-type lightly doped diffusion layers, said N-type heavily doped diffusion layers and said P-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment.
Claim 3
Dependent Claim
47 words
The method of manufacturing a CMOS transistor according to claim 1, wherein said gate electrodes have a laminated structure composed of a polycrystalline silicon to which an N-type or P-type impurity is doped and a silicide of a high-melting-point metal which is laminated on the polycrystalline silicon.
Claim 4
Independent Claim
275 words
A method of manufacturing a CMOS transistor, comprising the steps of: depositing, after a polycrystalline silicon layer is deposited on a semiconductor substrate with a gate insulating layer therebetween, a high-melting-point metal silicide layer on said polycrystalline silicon layer; forming, after a first insulating layer is deposited on said high-melting-point metal silicide layer, gate electrodes of an N-channel transistor and a P-channel transistor by dray-etching said high-melting-point metal silicide layer and said first insulating layer; depositing a second insulating layer on an upper surface and both side surfaces of said gate electrodes; forming N-type lightly doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode of the N-channel transistor as a mask; conducting a first thermal treatment to said gate electrode and the N-type lightly doped diffusion layers; forming P-type lightly doped diffusion layers to be a source or a drain of the P-channel transistor, using said gate electrode of the P-channel transistor as a mask; forming side walls on side surfaces of said gate electrodes; forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode and said side walls of the N-channel transistor as a mask; forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using said gate electrode and said side walls of the P-channel transistor as a mask; and conducting a second thermal treatment to said P-type lightly doped diffusion layers, said N-type heavily doped diffusion layers and said P-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment.
Claim 5
Independent Claim
275 words
A method of manufacturing a CMOS transistor, comprising the steps of: depositing, after a polycrystalline silicon layer is deposited on a semiconductor substrate with a gate insulating layer therebetween, a high-melting-point metal silicide layer on said polycrystalline silicon layer; forming, after a first insulating layer is deposited on said high-melting-point metal silicide layer, gate electrodes of an N-channel transistor and a P-channel transistor by dray-etching said high-melting-point metal silicide layer and said first insulating layer; depositing a second insulating layer on an upper surface and both side surfaces of said gate electrodes; forming N-type lightly doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode of the N-channel transistor as a mask; conducting a first thermal treatment to said gate electrode and the N-type lightly doped diffusion layers; forming P-type lightly doped diffusion layers to be a source or a drain of the P-channel transistor, using said gate electrode of the P-channel transistor as a mask; forming side walls on side surfaces of said gate electrodes; forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode and said side walls of the N-channel transistor as a mask; forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using said gate electrode and said side walls of the P-channel transistor as a mask; and conducting a second thermal treatment to said P-type lightly doped diffusion layers, said N-type heavily doped diffusion layers and said P-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment.
Claim 6
Independent Claim
247 words
A method of manufacturing a CMOS transistor, comprising the steps of: depositing, after a polycrystalline silicon layer is deposited on a semiconductor substrate with a gate insulating layer therebetween, a high-melting-point metal silicide layer on said polycrystalline silicon layer; forming, after a first insulating layer is deposited on said high-melting-point metal slliclde layer, gate electrodes of an N-channel transistor and a P-channel transistor by dray-etching said high-melting-point metal silicide layer and said first insulating layer; depositing a second insulating layer on an upper surface and both side surfaces of said gate electrodes; forming N-type lightly doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode of the N-channel transistor as a mask; conducting a first thermal treatment to said gate electrodes and said N-type lightly doped diffusion layers: forming side walls on side surfaces of said gate electrodes; forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode and said side walls of the N-channel transistor as a mask; forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using said gate electrode and said side walls of the P-channel transistor as a mask; and conducting a second thermal treatment to said P-type lightly doped diffusion layers, said N-type heavily doped diffusion layers and said P-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment.
Claim 7
Independent Claim
247 words
A method of manufacturing a CMOS transistor, comprising the steps of: depositing, after a polycrystalline silicon layer is deposited on a semiconductor substrate with a gate insulating layer therebetween, a high-melting-point metal silicide layer on said polycrystalline silicon layer; forming, after a first insulating layer is deposited on said high-melting-point metal slliclde layer, gate electrodes of an N-channel transistor and a P-channel transistor by dray-etching said high-melting-point metal silicide layer and said first insulating layer; depositing a second insulating layer on an upper surface and both side surfaces of said gate electrodes; forming N-type lightly doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode of the N-channel transistor as a mask; conducting a first thermal treatment to said gate electrodes and said N-type lightly doped diffusion layers: forming side walls on side surfaces of said gate electrodes; forming N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor, using said gate electrode and said side walls of the N-channel transistor as a mask; forming P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor, using said gate electrode and said side walls of the P-channel transistor as a mask; and conducting a second thermal treatment to said P-type lightly doped diffusion layers, said N-type heavily doped diffusion layers and said P-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment.
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