US5270233A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing field effect transistor having LDD structure
Assignee: NEC Electronics Corp
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Filing: 1992-06-24
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Granted: 1993-12-14
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Expires: 2012-06-24
Abstract
Abstract In a method for manufacturing a MOS transistor having the LDD structure, an N-channel MOS transistor of the LDD structure is obtained by forming a first silicon dioxide film on the side walls of a first gate electrode by utilizing a first photoresist film and a selective growth of a first LPD silicon dioxide film by liquid phase deposition, in order to reduce the number of photolithography processes. Similarly, a P-channel MOS transistor of the LDD structure is obtained by forming a second silicon dioxide film for spacer on the side walls of a second gate electrode by utilizing a second photoresist film and a selective growth of a second LDD silicon dioxide film by liquid phase deposition.
Inventors
- 👤 Nobuhisa Hamatake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:22
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
508 words
A method for manufacturing a CMOS transistor, comprising: a process of providing an oxide film for device isolation in predetermined regions on the surface of a semiconductor substrate having a region of one conductivity type and a region of the opposite conductivity type and forming a gate insulating film on the surface of said region of the one conductivity type and on the surface of said region of the opposite conductivity type; a process of providing a first gate electrode on said region of the one conductivity type via said gate insulating film and providing a second gate electrode on said region of the opposite conductivity type via said gate insulating film; a process of forming a first photoresist film which covers said region of the opposite conductivity type and has a first opening at least exposing said gate insulating film on the surface of said region of the one conductivity type; a process of forming a low concentration diffused layer of the opposite conductivity type in said region of the one conductivity type by an ion implantation which uses said first gate electrode and said first photoresist film as a mask; a process of selectively growing a first liquid phase deposited silicon dioxide film in said first opening by a liquid phase deposition method which uses said first photoresist film as a mask; a process of forming a first silicon dioxide film for spacer on the side walls of said first gate electrode by applying a reactive ion etching to said first liquid phase deposited silicon dioxide film; a process of forming a high concentration diffused layer of the opposite conductivity type in said region of the one conductivity type by an ion implantation which uses said first gate electrode and said first silicon dioxide film for spacer and said first photoresist film as a mask; a process of forming, after removing said first photoresist film, a second photoresist film which covers said region of one conductivity type and has a second opening at least exposing said gate insulating film on the surface of said region of the opposite conductivity type; a process of forming a low concentration diffused layer of the one conductivity type in said region of the opposite conductivity type by an ion implantation which uses said second gate electrode and said second photoresist film as a mask; a process of selectively growing a second liquid phase deposited silicon dioxide film in said second opening by a liquid phase deposition method which uses said second photoresist film as a mask; a process of forming a second silicon dioxide film for spacer on the side walls of said second gate electrode by applying a reactive ion etching to said second liquid phase deposited silicon dioxide film; and a process of forming a high concentration diffused layer of the one conductivity type in said region of the opposite conductivity type by an ion implantation which uses said second gate electrode and said second silicon dioxide film for spacer and said second photoresist film as a mask.
Claim 2
Independent Claim
508 words
A method for manufacturing a CMOS transistor, comprising: a process of providing an oxide film for device isolation in predetermined regions on the surface of a semiconductor substrate having a region of one conductivity type and a region of the opposite conductivity type and forming a gate insulating film on the surface of said region of the one conductivity type and on the surface of said region of the opposite conductivity type; a process of providing a first gate electrode on said region of the one conductivity type via said gate insulating film and providing a second gate electrode on said region of the opposite conductivity type via said gate insulating film; a process of forming a first photoresist film which covers said region of the opposite conductivity type and has a first opening at least exposing said gate insulating film on the surface of said region of the one conductivity type; a process of forming a low concentration diffused layer of the opposite conductivity type in said region of the one conductivity type by an ion implantation which uses said first gate electrode and said first photoresist film as a mask; a process of selectively growing a first liquid phase deposited silicon dioxide film in said first opening by a liquid phase deposition method which uses said first photoresist film as a mask; a process of forming a first silicon dioxide film for spacer on the side walls of said first gate electrode by applying a reactive ion etching to said first liquid phase deposited silicon dioxide film; a process of forming a high concentration diffused layer of the opposite conductivity type in said region of the one conductivity type by an ion implantation which uses said first gate electrode and said first silicon dioxide film for spacer and said first photoresist film as a mask; a process of forming, after removing said first photoresist film, a second photoresist film which covers said region of one conductivity type and has a second opening at least exposing said gate insulating film on the surface of said region of the opposite conductivity type; a process of forming a low concentration diffused layer of the one conductivity type in said region of the opposite conductivity type by an ion implantation which uses said second gate electrode and said second photoresist film as a mask; a process of selectively growing a second liquid phase deposited silicon dioxide film in said second opening by a liquid phase deposition method which uses said second photoresist film as a mask; a process of forming a second silicon dioxide film for spacer on the side walls of said second gate electrode by applying a reactive ion etching to said second liquid phase deposited silicon dioxide film; and a process of forming a high concentration diffused layer of the one conductivity type in said region of the opposite conductivity type by an ion implantation which uses said second gate electrode and said second silicon dioxide film for spacer and said second photoresist film as a mask.
Claim 3
Dependent Claim
73 words
A method for manufacturing a CMOS transistor as claimed in claim 1, which is characterized in that said first and said second liquid phase deposited silicon dioxide films are formed by a liquid phase deposition method by immersing the substrate in an aqueous solution of hydrofluorosilicic acid supersaturated with silicon dioxide formed by adding boric acid to an aqueous solution of hydrofluorosilicic acid in which silicon dioxide is dissolved in a saturated state.
Claim 4
Dependent Claim
36 words
A method for manufacturing a CMOS transistor as claimed in claim 1, wherein the thickness of said first silicon dioxide film for spacer is different from the thickness of said second silicon dioxide film for spacer.
Claim 5
Dependent Claim
43 words
A method for manufacturing a CMOS transistor as claimed in claim 1, further comprising a process of forming an insulating film on the surface of said first and said second gate electrodes after forming said first gate electrode and said second gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-12-13 | 1997-06-14 | 1997-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-13 | 2001-06-14 | 2001-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-13 | 2005-06-14 | 2005-12-14 | $7700.00 | Window Closed / Lapsed |