US5447872A
Expired / Lapsed
US
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Manufacturing method of CMOS transistor including heat treatments of gate electrodes and LDD regions at reducing temperatures
Assignee: Panasonic Holdings Corp
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Filing: 1994-11-14
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Granted: 1995-09-05
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Expires: 2014-11-14
Abstract
Abstract Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
Inventors
- 👤 Mizuki Segawa
- 👤 Yoshiaki Kato
- 👤 Hiroaki Nakaoka
- 👤 Takashi Nakabayashi
- 👤 Atsushi Hori
- 👤 Hiroshi Masuda
- 👤 Ichiro Matsuo
- 👤 Akihira Shinohara
- 👤 Takashi Uehara
- 👤 Mitsuo Yasuhira
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:19
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/147
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
227 words
A method of manufacturing a CMOS transistor, comprising the steps of: forming gate electrodes of an N-channel transistor and a P-channel transistor on a semiconductor substrate with a gate insulating layer therebetween; conducting a first thermal treatment to said gate electrodes; forming N-type lightly doped diffusion layers as a source or a drain of the N-channel transistor, using the gate electrode of the N-channel transistor as a mask; conducting a second thermal treatment to said N-type lightly doped diffusion layers at a lower temperature than that of the first thermal treatment; forming P-type lightly doped diffusion layers as a source or a drain of the P-channel transistor, using the gate electrode of the P-channel transistor as a mask; forming side walls on side surfaces of said gate electrodes; forming N-type heavily doped diffusion layers as a source or a drain of the N-channel transistor, using said gate electrode and said side walls of the N-channel transistor as a mask; forming P-type heavily doped diffusion layers as a source or a drain of the P-channel transistor, using said gate electrode and said side walls of the P-channel transistor as a mask; and conducting a third thermal treatment to said P-type lightly doped diffusion layers, said N-type heavily doped diffusion layers and said P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
Claim 2
Independent Claim
227 words
A method of manufacturing a CMOS transistor, comprising the steps of: forming gate electrodes of an N-channel transistor and a P-channel transistor on a semiconductor substrate with a gate insulating layer therebetween; conducting a first thermal treatment to said gate electrodes; forming N-type lightly doped diffusion layers as a source or a drain of the N-channel transistor, using the gate electrode of the N-channel transistor as a mask; conducting a second thermal treatment to said N-type lightly doped diffusion layers at a lower temperature than that of the first thermal treatment; forming P-type lightly doped diffusion layers as a source or a drain of the P-channel transistor, using the gate electrode of the P-channel transistor as a mask; forming side walls on side surfaces of said gate electrodes; forming N-type heavily doped diffusion layers as a source or a drain of the N-channel transistor, using said gate electrode and said side walls of the N-channel transistor as a mask; forming P-type heavily doped diffusion layers as a source or a drain of the P-channel transistor, using said gate electrode and said side walls of the P-channel transistor as a mask; and conducting a third thermal treatment to said P-type lightly doped diffusion layers, said N-type heavily doped diffusion layers and said P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
Claim 3
Dependent Claim
47 words
The method of manufacturing a CMOS transistor according to claim 1, wherein said gate electrodes have a laminated structure composed of a polycrystalline silicon to which an N-type or P-type impurity is doped and a silicide of a high-melting-point metal which is laminated on the polycrystalline silicon.
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| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
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| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |