Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices

Claim 1

In an integrated circuit wafer having a substrate with gate regions and field oxide regions formed thereon, a method for doping source and drain regions for sub-half-micron devices in the substrate adjacent the top surface thereof on opposing sides of each gate region, comprising the steps of: forming oxide spacers surrounding said gate regions; forming lightly doped graded regions in the source and drain regions having a doping concentration that decreases linearly with distance from the top surface of the source and drain regions; and forming respective heavily doped regions in each of the lightly doped graded regions adjacent the surface of the source and drain regions.

Claim 5

A method of fabricating sub-half-micron integrated circuits comprising: providing a semiconductor substrate of a first conductivity type; forming a layer of oxide on the semiconductor substrate; forming a gate of semiconductor material of said first conductivity type on said oxide layer on a predefined region; forming an oxide spacer surrounding said gate; implanting first ions of a second conductivity type at a dose equal to or greater than about 1×10 12 ions/cm 2 and less than about 1×10 15 ions/cm 2; heating said substrate to a first predetermined temperature for a first predetermined time; implanting second ions of a second conductivity type at a dose equal to or greater than about 1×10 15 ions/cm 2 and less than about 1×10 17 ions/cm 2; and heating said substrate to a second predetermined temperature for a second predetermined period of time sufficient to activate the implants.

Claim 6

A method of fabricating sub-half-micron integrated circuits comprising: providing a semiconductor substrate of a first conductivity type; forming a layer of oxide on the semiconductor substrate; forming a gate of semiconductor material of said first conductivity type on said oxide layer on a predefined region; forming an oxide spacer surrounding said gate; implanting first ions of a second conductivity type at a dose equal to or greater than about 1×10 12 ions/cm 2 and less than about 1×10 15 ions/cm 2; heating said substrate to a first predetermined temperature for a first predetermined time; implanting second ions of a second conductivity type at a dose equal to or greater than about 1×10 15 ions/cm 2 and less than about 1×10 17 ions/cm 2; and heating said substrate to a second predetermined temperature for a second predetermined period of time sufficient to activate the implants.

Claim 12

A method for forming a sub-half-micron semiconductor integrated circuit, comprising the steps of: providing a semiconductor substrate having a first surface; forming an oxide layer on the first surface of the semiconductor substrate; disposing a gate made of semiconductor material on said oxide layer; forming an oxide spacer surrounding said gate; forming first source and drain regions in said substrate adjacent said first surface and on opposite sides of said gate wherein said first source and drain regions have a doping concentration that decreases linearly with distance from the top surface of said first source and drain regions; and forming second heavily doped source and drain region on opposite sides of said gate respectively within said first source and drain regions.

Claim 13

A method for forming a sub-half-micron semiconductor integrated circuit, comprising the steps of: providing a semiconductor substrate having a first surface; forming an oxide layer on the first surface of the semiconductor substrate; disposing a gate made of semiconductor material on said oxide layer; forming an oxide spacer surrounding said gate; forming first source and drain regions in said substrate adjacent said first surface and on opposite sides of said gate wherein said first source and drain regions have a doping concentration that decreases linearly with distance from the top surface of said first source and drain regions; and forming second heavily doped source and drain region on opposite sides of said gate respectively within said first source and drain regions.