US4874713A
Expired / Lapsed
US
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Method of making asymmetrically optimized CMOS field effect transistors
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1989-05-01
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Granted: 1989-10-17
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Expires: 2009-05-01
Abstract
Abstract A process for forming an asymmetrically structured pair of CMOS field effect transistors having feature refinements matched to the individual idiosyncrasies of the p-channel and n-channel transistors. Complementary transistors are formed using a single photolithographic mask and a fabrication sequence which begins with the p-channel transistor source/drain formation. Thereafter, the p-channel transistor source/drain regions are metalized, the n-channel transistor lightly doped drain regions are formed, and the sidewall dielectric spaced n-channel transistor source/drain regions are formed using the p-channel metalization as a mask. The p-channel transistor source/drain metalization suppresses the effects of the relatively greater p-type source/drain resistivity, while the LDD structure of the n-channel transistor reduces performance degradation attributable to hot electron trapping. The structural asymmetry attributable to the process materially offsets performance limitations common to the individual CMOS transistor types.
Inventors
- 👤 Samuel C. Gioia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
156 words
A process for forming CMOS field effect transistor integrated circuits, comprising the steps of: forming in an active region of a semiconductor substrate first and second polysilicon gate electrodes with underlying gate dielectrics; forming a capping dielectric layer over the first and second polysilicon gate electrodes; forming a photolithographic mask over the second polysilicon gate electrode and associated field effect transistor source/drain regions; doping the substrate in the presence of the photolithographic mask to form source/drain regions in the semiconductor substrate aligned to the first polysilicon gate electrode; selectively forming metallic regions over the source/drain regions of the first polysilicon gate electrode; thereafter lightly doping source/drain regions of the second polysilicon gate electrode in alignment with the second polysilicon gate electrode using said metallic regions as a mask; forming a sidewall dielectric for the second polysilicon gate electrode; and heavily doping the source/drain region of the second polysilicon gate electrode in alignment with the sidewall dielectric.
Claim 2
Dependent Claim
156 words
A process for forming CMOS field effect transistor integrated circuits, comprising the steps of: forming in an active region of a semiconductor substrate first and second polysilicon gate electrodes with underlying gate dielectrics; forming a capping dielectric layer over the first and second polysilicon gate electrodes; forming a photolithographic mask over the second polysilicon gate electrode and associated field effect transistor source/drain regions; doping the substrate in the presence of the photolithographic mask to form source/drain regions in the semiconductor substrate aligned to the first polysilicon gate electrode; selectively forming metallic regions over the source/drain regions of the first polysilicon gate electrode; thereafter lightly doping source/drain regions of the second polysilicon gate electrode in alignment with the second polysilicon gate electrode using said metallic regions as a mask; forming a sidewall dielectric for the second polysilicon gate electrode; and heavily doping the source/drain region of the second polysilicon gate electrode in alignment with the sidewall dielectric.
Claim 3
Dependent Claim
57 words
The process recited in claim 1, wherein the forming of a capping dielectric layer involves an oxide growth characterized by a differential oxidation rate between the silicon substrate and the gate electrode polysilicon, and the further step of removing grown silicon dioxide from source/drain regions aligned to the first polysilicon gate electrode before removing the photolithographic mask.
Claim 4
Dependent Claim
40 words
The process recited in claim 2, wherein a capping layer of silicon dioxide is retained over the first polysilicon gate electrode following the removal of the grown silicon dioxide from the source/drain regions aligned to the first polysilicon gate electrode.
Claim 5
Dependent Claim
21 words
The process recited in claim 3, wherein the selective formation of metallic regions involves a selective deposition of a refractory metal.
Claim 6
Dependent Claim
43 words
The process recited in claim 3, wherein the selective formation of metallic regions involves the steps of: blanket depositing a metal layer; conditioning the substrate to selectively react the deposited metal with substrate silicon in the source/drain regions; and selectively removing unreacted metal.
Claim 7
Dependent Claim
34 words
The process recited in claim 4, wherein the sidewall dielectric for the second polysilicon gate electrode is formed by: conformally depositing silicon dioxide; and anisotropically etching the silicon dioxide to expose the source/drain region.
Claim 8
Dependent Claim
34 words
The process recited in claim 5, wherein the sidewall dielectric for the second polysilicon gate electrode is formed by: conformally depositing silicon dioxide; and anisotropically etching the silicon dioxide to expose the source/drain region.
Claim 9
Dependent Claim
30 words
The process recited in claim 6, wherein the first polysilicon gate electrode defines a p-channel field effect transistor and the second polysilicon gate electrode defines an n-channel field effect transistor.
Claim 10
Dependent Claim
30 words
The process recited in claim 7, wherein the first polysilicon gate electrode defines a p-channel field effect transistor and the second polysilicon gate electrode defines an n-channel field effect transistor.
Claim 11
Dependent Claim
36 words
The process recited in claim 8, wherein the light doping of the source/drain region in alignment with the second polysilicon gate uses n-type impurity to form an LDD region aligned to the second polysilicon gate electrode.
Claim 12
Dependent Claim
36 words
The process recited in claim 9, wherein the light doping of the source/drain region in alignment with the second polysilicon gate uses n-type impurity to form an LDD region aligned to the second polysilicon gate electrode.
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