US4830971A
Expired / Lapsed
US
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Method for manufacturing a semiconductor device utilizing self-aligned contact regions
Assignee: Toshiba Corp
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Filing: 1986-02-25
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Granted: 1989-05-16
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Expires: 2006-02-25
Abstract
Abstract A method for manufacturing a semiconductor device of the invention comprises the steps of (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film; (b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate; (c) forming a self-aligned insulating layer on the side walls of the gate electrode; (d) forming a self-aligned metal layer on a region on which an insulating film is not formed, the region including the source region and the drain region; and (e) forming electrodes which are connected to the source region, drain region and gate electrode.
Inventors
- 👤 Tadashi Shibata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0212; H10D30/0227; H10D30/60; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/015; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/62; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; H10W; H10W20/00; H10W20/01; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S148/02; Y10S148/106; Y10S148/139; Y10S148/141; Y10S148/147; Y10S148/156; Y10S257/00; Y10S257/902
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
136 words
A method for manufactoring a semiconductor device, comprising the steps of: (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulation film; (b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate; (c) forming an insulating layer on said substrate and etching the insulating layer by an anistropic etching thus leaving the self-aligned insulating layer on the side walls of said gate electrode; (d) forming a self-aligned metal layer on a region on which an insulating film is not formed, said region including said source region and said drain region; and (e) forming electrodes which are connected to the source region,drain region and gate electrode.
Claim 2
Independent Claim
136 words
A method for manufactoring a semiconductor device, comprising the steps of: (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulation film; (b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate; (c) forming an insulating layer on said substrate and etching the insulating layer by an anistropic etching thus leaving the self-aligned insulating layer on the side walls of said gate electrode; (d) forming a self-aligned metal layer on a region on which an insulating film is not formed, said region including said source region and said drain region; and (e) forming electrodes which are connected to the source region,drain region and gate electrode.
Claim 3
Dependent Claim
18 words
A method according to claim 1, wherein said anisotropic etching method is reactive ion etching or sputtering etching.
Claim 4
Dependent Claim
26 words
A method according to claim 2, further including the step of etching a surface of said silicon substrate which is exposed by the anisotropic etching method.
Claim 5
Dependent Claim
36 words
A method according to claim 1, further including the step of performing phosphorus gettering in an atmosphere at high temperature containing phosphorus, after said insulating film is formed to cover the entire surface of the substrate.
Claim 6
Dependent Claim
50 words
A method according to claim 1, wherein said gate electrode is a polycrystalline silicon layer in which an impurity of high concentraiton is doped, and step (c) includes oxidation in a wet or stream atmosphere, etching, and leaving an oxide film only on the side surface of said gate electrode.
Claim 7
Dependent Claim
59 words
A method according to claim 1, wherein step (d) includes the steps of heating said silicon substrate at a temperature lower than a temperature for forming an alloy of the silicon and metal, surrounding said silicon substrate with a metal halide gas and a reducing gas, and depositing a metal film on the exposed surface of said silicon substrate.
Claim 8
Dependent Claim
26 words
A method according to claim 1, wherein the metal is a member selected from the group consisting of W, Pd, Pt, Ni, Mo, Nd and Ta.
Claim 9
Dependent Claim
43 words
A method according to claim 1, further comprising the steps of doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate at a dose higher than that in the doping in step (b).
Claim 10
Independent Claim
138 words
A method for manufactoring a semiconductor device, comprising the steps of: (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulation film; (b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate; (c) forming an insulating layer on said substrate and etching the insulating layer by an anistropic etching thus leaving the self-aligned insulating layer on the side walls of said gate electrode; (d) forming a self-aligned metal silicide layer on a region on which an insulating film is not formed, said region including said source region and said drain region; and (e) forming electrodes which are connected to the source region, drain region and gate electrode.
Claim 11
Independent Claim
138 words
A method for manufactoring a semiconductor device, comprising the steps of: (a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulation film; (b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate; (c) forming an insulating layer on said substrate and etching the insulating layer by an anistropic etching thus leaving the self-aligned insulating layer on the side walls of said gate electrode; (d) forming a self-aligned metal silicide layer on a region on which an insulating film is not formed, said region including said source region and said drain region; and (e) forming electrodes which are connected to the source region, drain region and gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |