US4503601A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Oxide trench structure for polysilicon gates and interconnects
Assignee: MagnaChip Semiconductor Ltd
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Filing: 1983-04-18
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Granted: 1985-03-12
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Expires: 2003-04-18
Abstract
Abstract Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate. In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation. Then, low temperature thermal oxidation is accomplished growing a thick oxide over the polysilicon gate sidewalls and a thin oxide over the source-drain regions. The mask over the gate and the thin oxide over the source-drain regions is removed and by ion implantation heavily doped source-drain regions are formed in the previously formed lightly doped source-drain regions not masked by the polysilicon sidewall oxide. Selective deposition of a metal is then accomplished over the source-drain regions of the silicon substrate and the polysilicon gate.
Inventors
- 👤 Samuel Y. Chiao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:29
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0215; H10D30/0229; H10D30/60; H10D30/601; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/02; H10D84/03; H10D84/038; H10P; H10P76/00; H10P76/40; H10P76/408; H10P76/4085; H10P95/00; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; Y; Y10; Y10S; Y10S438/00; Y10S438/911
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
149 words
A process for forming a metal covered high conductivity region of a substrate and a metal covered polysilicon conductor in close proximity to said region, said process comprising: forming said polysilicon conductor on selected portions of said substrate from a highly doped polysilicon layer having a masking member thereon; thermally oxidizing at a relatively low temperature in the range of 700-750 degrees C. for a time sufficient to form a relatively thick oxide layer on the side surfaces of said polysilicon conductor and a relatively thin oxide layer on the uncovered portions of said substrate; removing the relatively thin oxide layer on said uncovered portions of said substrate; doping said uncovered portions of said substrate to a high conductivity; removing the masking member to expose the upper surface of said polysilicon conductor; and forming a metal layer over said exposed, highly doped portion of said substrate and polysilicon conductor.
Claim 2
Dependent Claim
149 words
A process for forming a metal covered high conductivity region of a substrate and a metal covered polysilicon conductor in close proximity to said region, said process comprising: forming said polysilicon conductor on selected portions of said substrate from a highly doped polysilicon layer having a masking member thereon; thermally oxidizing at a relatively low temperature in the range of 700-750 degrees C. for a time sufficient to form a relatively thick oxide layer on the side surfaces of said polysilicon conductor and a relatively thin oxide layer on the uncovered portions of said substrate; removing the relatively thin oxide layer on said uncovered portions of said substrate; doping said uncovered portions of said substrate to a high conductivity; removing the masking member to expose the upper surface of said polysilicon conductor; and forming a metal layer over said exposed, highly doped portion of said substrate and polysilicon conductor.
Claim 3
Dependent Claim
16 words
The process as in claim 1 wherein said masking member is a layer of silicon nitride.
Claim 4
Dependent Claim
216 words
A process for forming a lightly doped drain polysilicon gate n-MOSFET on a p-type semiconductor silicon substrate having an active region covered by a relatively thin silicon dioxide layer, said process comprising: forming a highly doped polysilicon layer over th silicon dioxide layer; forming a mask over the polysilicon; patterning the polysilicon in the presence of a mask to form a polysilicon gate on said active region; removing said oxide layer outside a gate region dfined by said gate on the active region; implanting n-type ions at a relatively low dose and energy in source and drain regions defined in said active region by the gate and mask thereon; thermally oxidizing at a relatively low temperature of about 700-750 degrees C. for a time sufficient to form a relatively thick oxide layer on the side surfaces of said polysilicon gate and a relatively thin oxide layer in the previously defined source and drain regions of the substrate; removing said mask over the polysilicon and said thin oxide over the source and drain regions; implanting n-type ions of a relatively high dose and energy in said source and drain regions not masked by said thick oxide and said polysilicon gate; and selectively depositing a metal layer over the exposed polysilicon gate and the source and drain regions.
Claim 5
Dependent Claim
216 words
A process for forming a lightly doped drain polysilicon gate n-MOSFET on a p-type semiconductor silicon substrate having an active region covered by a relatively thin silicon dioxide layer, said process comprising: forming a highly doped polysilicon layer over th silicon dioxide layer; forming a mask over the polysilicon; patterning the polysilicon in the presence of a mask to form a polysilicon gate on said active region; removing said oxide layer outside a gate region dfined by said gate on the active region; implanting n-type ions at a relatively low dose and energy in source and drain regions defined in said active region by the gate and mask thereon; thermally oxidizing at a relatively low temperature of about 700-750 degrees C. for a time sufficient to form a relatively thick oxide layer on the side surfaces of said polysilicon gate and a relatively thin oxide layer in the previously defined source and drain regions of the substrate; removing said mask over the polysilicon and said thin oxide over the source and drain regions; implanting n-type ions of a relatively high dose and energy in said source and drain regions not masked by said thick oxide and said polysilicon gate; and selectively depositing a metal layer over the exposed polysilicon gate and the source and drain regions.
Claim 6
Dependent Claim
67 words
The process as recited in claim 3 further comprising the steps of: patterning the polysilicon in the presence of the mask to form interconnecting conductors simultaneously with the patterning of the polysilicon into a gate; forming a thick oxide layer on the side surfaces of the conductors during said thermal oxidation step; and selectively depositing a metal layer over the polysilicon interconnects during said metal deposition step.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-11 | 1988-09-10 | 1989-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-11 | 1992-09-10 | 1993-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-11 | 1996-09-10 | 1997-03-12 | $7700.00 | Window Closed / Lapsed |