Double polysilicon electrostatic discharge protection device for SRAM and DRAM memory devices

Claim 1

A semiconductor electrostatic discharge device adapted for inclusion in a semiconductor memory system, formed on a semiconductor substrate covered with silicon dioxide and field oxide regions, comprising a first layer composed of a material selected from polysilicon and polycide having a surface, said surface of said device including thereon silicon dioxide and field oxide regions, said first layer having been patterned into a first gate in a first area and a second gate in a standard device area, said first area and said second area separated by a field oxide region, lightly doped implantation regions in said substrate adjacent to said gate in said standard device area, spacers adjacent to said periphery of said said second gate, dopant adjacent to said spacers forming source/drain regions adjacent to second gate, an interpolysilicon region over said standard device area, a second layer composed of a material selected from polysilicon and polycide formed upon said first area and said second layer stacked upon said first layer of said first gate, and second source/drain regions in said substrate adjacent to said first gate being doped.

Claim 5

A method of manufacture of a semiconductor electrostatic discharge protection device adapted for inclusion in a semiconductor memory system, formed on a semiconductor substrate covered with silicon dioxide regions and field oxide regions between said silicon dioxide regions, comprising formation of a blanket first gate element layer on said surface of said device including said silicon dioxide and field oxide regions, patterning said first gate layer into a first gate element without spacers for a first device overlying portions of said field oxide regions and a second gate element with spacers in a standard device area said first gate element and said second gate element separated by field oxide regions, formation of lightly doped drain implantation into said substrate adjacent to said second gate element in said standard device area, formation of spacers adjacent to said periphery of said first gate element and said second gate element, ion implanting dopant adjacent to said spacers to form source/drain regions adjacent to said second gate of said standard device, formation of an interpolysilicon dielectric layer over said device, formation of a polysilicon via mask over said standard device area and etching away said interpolysilicon dielectric layer over said first gate element to form a via opening through areas unprotected by said mask, deposition of a blanket second gate layer shorted to said first gate element and forming a masking layer and etching away exposed areas of said second gate layer and said first gate element leaving a stacked structure from portions of said first gate element and said second gate layer, removal of said masking layer, and formation of a mask and performing a doping process doping said second layer and second source/drain regions in said substrate adjacent to said first gate, whereby Lightly Doped Drain (LDD) technology includes Input/Output Electrostatic Discharge (ESD) protection without the burden of providing one extra masking step to secure the desired protection.

Claim 6

A method of manufacture of a semiconductor electrostatic discharge protection device adapted for inclusion in a semiconductor memory system, formed on a semiconductor substrate covered with silicon dioxide regions and field oxide regions between said silicon dioxide regions, comprising formation of a blanket first gate element layer on said surface of said device including said silicon dioxide and field oxide regions, patterning said first gate layer into a first gate element without spacers for a first device overlying portions of said field oxide regions and a second gate element with spacers in a standard device area said first gate element and said second gate element separated by field oxide regions, formation of lightly doped drain implantation into said substrate adjacent to said second gate element in said standard device area, formation of spacers adjacent to said periphery of said first gate element and said second gate element, ion implanting dopant adjacent to said spacers to form source/drain regions adjacent to said second gate of said standard device, formation of an interpolysilicon dielectric layer over said device, formation of a polysilicon via mask over said standard device area and etching away said interpolysilicon dielectric layer over said first gate element to form a via opening through areas unprotected by said mask, deposition of a blanket second gate layer shorted to said first gate element and forming a masking layer and etching away exposed areas of said second gate layer and said first gate element leaving a stacked structure from portions of said first gate element and said second gate layer, removal of said masking layer, and formation of a mask and performing a doping process doping said second layer and second source/drain regions in said substrate adjacent to said first gate, whereby Lightly Doped Drain (LDD) technology includes Input/Output Electrostatic Discharge (ESD) protection without the burden of providing one extra masking step to secure the desired protection.