Structure of input protection transistor in semiconductor device including memory transistor having double-layered gate and method of manufacturing semiconductor device including such input protection transistor

Claim 1

A semiconductor device having an internal circuit including a memory device, and an input protection device for protecting said internal circuit, both said internal circuit and said input protection device being formed on one semiconductor substrate; wherein said input protection device comprises: source and drain impurity regions formed only of high concentration impurity regions, spaced apart from each other in a surface of said semiconductor substrate; a first insulator film formed on the surface of said semiconductor substrate between said source and drain impurity regions; a first electrode formed on said first insulator film; a second insulator film formed on said first electrode; a second electrode formed on said second insulator film; one region of said source and drain impurity regions of said input protection device being electrically connected to an interconnection for supplying an electrical signal to said internal circuit; the other region of said source and drain impurity regions of said input protection device and said semiconductor substrate being connected to a ground terminal; one of said first and second electrodes of said input protection device being connected by a conducting material to the ground terminal; and the other of said first and second electrodes being connected by a conducting material to said interconnection for supplying an electrical signal.