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US5142345A
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Structure of input protection transistor in semiconductor device including memory transistor having double-layered gate and method of manufacturing semiconductor device including such input protection transistor
Assignee: Mitsubishi Electric Corp
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Filing: 1991-08-15
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Granted: 1992-08-25
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Expires: 2011-08-15
Abstract
Abstract Disclosed is a structure of a semiconductor device in which an internal circuit including a memory device and a transistor having an LDD structure, and an input protection device for protecting the internal circuit are formed on one semiconductor substrate, and a method of manufacturing such a semiconductor device. The input protection device and the memory device are formed at the same time. The input protection device as well as the memory device includes source/drain regions formed of high concentration impurity regions and formed in the surface of the semiconductor substrate, and a gate electrode formed of a plurality of conductor films and formed on the surface of the semiconductor substrate between the source/drain regions. When an abnormal voltage is applied to an interconnection for supplying an electrical signal to the internal circuit, a charge flows from the interconnection through one source/drain region of the input protection device into the semiconductor substrate, so that the internal circuit is protected against an excessive charge.
Inventors
- 👤 Kazuaki Miyata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:40
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
211 words
A semiconductor device having an internal circuit including a memory device, and an input protection device for protecting said internal circuit, both said internal circuit and said input protection device being formed on one semiconductor substrate; wherein said input protection device comprises: source and drain impurity regions formed only of high concentration impurity regions, spaced apart from each other in a surface of said semiconductor substrate; a first insulator film formed on the surface of said semiconductor substrate between said source and drain impurity regions; a first electrode formed on said first insulator film; a second insulator film formed on said first electrode; a second electrode formed on said second insulator film; one region of said source and drain impurity regions of said input protection device being electrically connected to an interconnection for supplying an electrical signal to said internal circuit; the other region of said source and drain impurity regions of said input protection device and said semiconductor substrate being connected to a ground terminal; one of said first and second electrodes of said input protection device being connected by a conducting material to the ground terminal; and the other of said first and second electrodes being connected by a conducting material to said interconnection for supplying an electrical signal.
Claim 2
Dependent Claim
211 words
A semiconductor device having an internal circuit including a memory device, and an input protection device for protecting said internal circuit, both said internal circuit and said input protection device being formed on one semiconductor substrate; wherein said input protection device comprises: source and drain impurity regions formed only of high concentration impurity regions, spaced apart from each other in a surface of said semiconductor substrate; a first insulator film formed on the surface of said semiconductor substrate between said source and drain impurity regions; a first electrode formed on said first insulator film; a second insulator film formed on said first electrode; a second electrode formed on said second insulator film; one region of said source and drain impurity regions of said input protection device being electrically connected to an interconnection for supplying an electrical signal to said internal circuit; the other region of said source and drain impurity regions of said input protection device and said semiconductor substrate being connected to a ground terminal; one of said first and second electrodes of said input protection device being connected by a conducting material to the ground terminal; and the other of said first and second electrodes being connected by a conducting material to said interconnection for supplying an electrical signal.
Claim 3
Dependent Claim
14 words
The semiconductor device of claim 1, wherein said internal circuit further comprises a transistor.
Claim 4
Dependent Claim
13 words
The semiconductor device of claim 2, wherein said transistor has an LDD structure.
Claim 5
Dependent Claim
82 words
The semiconductor device of claim 1, wherein said memory device comprises: source and drain impurity regions formed only of high concentration impurity regions, spaced apart from each other in a surface of said semiconductor substrate; a first insulator film formed on the surface of said semiconductor substrate between said source and drain impurity regions; a first electrode formed on said first insulator film; a second insulator film formed on said first electrode; and a second electrode formed on said second insulator film.
Claim 6
Dependent Claim
30 words
The semiconductor device of claim 1, wherein said first electrode is connected to the ground terminal and said second electrode is connected to said interconnection for supplying an electrical signal.
Claim 7
Dependent Claim
183 words
A semiconductor device having an internal circuit including a memory device, and an input protection device for protecting said internal circuit, both said internal circuit and said input protection device being formed on one semiconductor substrate; wherein said input protection device comprises: source and drain impurity regions formed only of high concentration impurity regions, spaced apart from each other in a surface of said semiconductor substrate; a first insulator film formed on the surface of said semiconductor substrate between said source and drain impurity regions; a first electrode formed on said first insulator film; a second insulator film formed on said first electrode; a second electrode formed on said second insulator film; one region of said source and drain impurity regions of said input protection device being electrically connected to an interconnection for supplying an electrical signal to said internal circuit; the other region of said source and drain impurity regions of said input protection device and said semiconductor substrate being connected to a ground terminal; and said first and second electrodes of said input protection device being connected to the ground terminal.
Claim 8
Dependent Claim
183 words
A semiconductor device having an internal circuit including a memory device, and an input protection device for protecting said internal circuit, both said internal circuit and said input protection device being formed on one semiconductor substrate; wherein said input protection device comprises: source and drain impurity regions formed only of high concentration impurity regions, spaced apart from each other in a surface of said semiconductor substrate; a first insulator film formed on the surface of said semiconductor substrate between said source and drain impurity regions; a first electrode formed on said first insulator film; a second insulator film formed on said first electrode; a second electrode formed on said second insulator film; one region of said source and drain impurity regions of said input protection device being electrically connected to an interconnection for supplying an electrical signal to said internal circuit; the other region of said source and drain impurity regions of said input protection device and said semiconductor substrate being connected to a ground terminal; and said first and second electrodes of said input protection device being connected to the ground terminal.
References Cited (Backward Citations)
JPS5745975A
Cited
GB2152284A
Cited
US4835597A
Cited
US4774421A
Cited
US4663645A
Cited
JPS6187373A
Cited
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