US5884068A
Expired / Lapsed
US
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Integrated circuit having a core which operates at a speed greater than the frequency of the bus
Assignee: Intel Corp
•
Filing: 1997-04-09
•
Granted: 1999-03-16
•
Expires: 2017-04-09
Abstract
Abstract A microprocessor that operates at the speed of the the bus or at a speed which is a multiple of the bus speed-on a selectable basis. The microprocessor includes a phase locked loop to generate clock signals for operations within the microprocessor and bus clock signals for data transfer operations on the bus. The present invention allows a microprocessor core to operate at the same frequency or twice the frequency of the address/data buses.
Inventors
- 👤 James W. Conary
- 👤 Robert R. Beutler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 05:15
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F13/00; G06F13/38; G06F1/00; G06F1/04; G06F1/08; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/3237; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835; G06F12/0891; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/30083; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
145 words
An integrated circuit for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said integrated circuit comprising: a clock generator to generate at least one core clock signal at a second frequency that is faster than the first frequency and having clock pulse widths equal in length to that of clock pulses of said at least one bus clock signal; a core coupled to the clock generator to perform operations in response to said at least one core clock signal; and a bus controller coupled to the clock generator, the core and the bus to transfer data between the core and the bus in accordance with said at least one bus clock signal while the core and the bus controller operate at the clock speed of said at least one core clock signal.
Claim 2
Dependent Claim
145 words
An integrated circuit for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said integrated circuit comprising: a clock generator to generate at least one core clock signal at a second frequency that is faster than the first frequency and having clock pulse widths equal in length to that of clock pulses of said at least one bus clock signal; a core coupled to the clock generator to perform operations in response to said at least one core clock signal; and a bus controller coupled to the clock generator, the core and the bus to transfer data between the core and the bus in accordance with said at least one bus clock signal while the core and the bus controller operate at the clock speed of said at least one core clock signal.
Claim 3
Dependent Claim
19 words
The integrated circuit defined by claim 1 wherein the second frequency is an integer multiple of the first frequency.
Claim 4
Dependent Claim
31 words
The integrated circuit defined by claim 2 wherein the integer multiple is two, such that the second frequency of said at least one core clock signal is twice the first frequency.
Claim 5
Dependent Claim
16 words
The integrated circuit defined by claim 1 wherein the second frequency is twice the first frequency.
Claim 6
Dependent Claim
16 words
The integrated circuit defined by claim 1 wherein the clock generator comprises a phase locked loop.
Claim 7
Dependent Claim
283 words
An integrated circuit for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said integrated circuit comprising: a clock generator to generate at least one core clock signal at a second frequency that is faster than the first frequency and having clock pulse widths equal in length to that of clock pulses of said at least one bus clock signal; a core coupled to the clock generator to perform operations in response to said at least one core clock signal; and a bus controller coupled to the clock generator, the core and the bus to transfer data between the core and the bus in accordance with said at least one bus clock signal while the core and the bus controller operate at the clock speed of said at least one core clock signal; wherein the clock generator comprises a phase locked loop comprising a phase detector to receive an external clock signal and a feedback signal and to generate a first signal in response thereto that is a measure of a phase difference between the external clock signal and the feedback signal; a voltage generator to generate a voltage control signal in accordance with the first signal; a voltage-controlled oscillator to generate said at least one core clock signal in response to the voltage control signal; and a frequency divider to generate the feedback signal in response to said at least one core clock signal, said feedback signal having a frequency which is a multiple of said at least one core clock signal, such that the oscillator produces a signal which is N times the frequency of the external clock signal.
Claim 8
Dependent Claim
283 words
An integrated circuit for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said integrated circuit comprising: a clock generator to generate at least one core clock signal at a second frequency that is faster than the first frequency and having clock pulse widths equal in length to that of clock pulses of said at least one bus clock signal; a core coupled to the clock generator to perform operations in response to said at least one core clock signal; and a bus controller coupled to the clock generator, the core and the bus to transfer data between the core and the bus in accordance with said at least one bus clock signal while the core and the bus controller operate at the clock speed of said at least one core clock signal; wherein the clock generator comprises a phase locked loop comprising a phase detector to receive an external clock signal and a feedback signal and to generate a first signal in response thereto that is a measure of a phase difference between the external clock signal and the feedback signal; a voltage generator to generate a voltage control signal in accordance with the first signal; a voltage-controlled oscillator to generate said at least one core clock signal in response to the voltage control signal; and a frequency divider to generate the feedback signal in response to said at least one core clock signal, said feedback signal having a frequency which is a multiple of said at least one core clock signal, such that the oscillator produces a signal which is N times the frequency of the external clock signal.
Claim 9
Dependent Claim
86 words
The integrated circuit defined by claim 6 wherein the frequency divider comprises: first logic to generate a masking signal in response to one of said at least one core clock signal, said masking signal being at a first state or a second state; and a second logic to generate the feedback signal in response to said one core clock signal and the masking signal when the masking signal is in the first state and masks the feedback signal the masking signal is in the second state.
Claim 10
Dependent Claim
126 words
A processor for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said processor comprising: a clock generator to generate at least of core clock signal at a second frequency that is faster than the first frequency; a CPU core coupled to the clock generator to execute instructions in response to said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus to transfer data between the CPU core and the bus in response to said at least one bus clock signal while the CPU core and the bus controller operate at the clock speed of said at least one core clock signal.
Claim 11
Dependent Claim
126 words
A processor for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said processor comprising: a clock generator to generate at least of core clock signal at a second frequency that is faster than the first frequency; a CPU core coupled to the clock generator to execute instructions in response to said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus to transfer data between the CPU core and the bus in response to said at least one bus clock signal while the CPU core and the bus controller operate at the clock speed of said at least one core clock signal.
Claim 12
Dependent Claim
18 words
The processor defined by claim 8 wherein the second frequency is an integer multiple of the first frequency.
Claim 13
Dependent Claim
30 words
The processor defined by claim 9 wherein the integer multiple is two, such that the second frequency of said at least one core clock signal is twice the first frequency.
Claim 14
Dependent Claim
15 words
The processor defined by claim 8 wherein the second frequency is twice the first frequency.
Claim 15
Dependent Claim
15 words
The processor defined by claim 8 wherein the clock generator comprises a phase locked loop.
Claim 16
Dependent Claim
264 words
A processor for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said processor comprising: a clock generator to generate at least of core clock signal at a second frequency that is faster than the first frequency; a CPU core coupled to the clock generator to execute instructions in response to said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus to transfer data between the CPU core and the bus in response to said at least one bus clock signal while the CPU core and the bus controller operate at the clock speed of said at least one core clock signal; wherein the clock generator comprises a phase locked loop comprising a phase detector to receive an external clock signal and a feedback signal and to generate a first signal in response thereto that is a measure of on phase difference between the external clock signal and the feedback signal; a voltage generator to generate a voltage control signal in accordance with the first signal; a voltage-controlled oscillator to generate said at least one core clock signal in response to the voltage control signal; and a frequency divider to generate the feedback signal in response to said at least one core clock signal, said feedback signal having a frequency which is a multiple of said at least one core clock signal, such that the oscillator produces a signal which is N times the frequency of the external clock signal.
Claim 17
Dependent Claim
264 words
A processor for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said processor comprising: a clock generator to generate at least of core clock signal at a second frequency that is faster than the first frequency; a CPU core coupled to the clock generator to execute instructions in response to said at least one core clock signal; and a bus controller coupled to the clock generator, the CPU core and the bus to transfer data between the CPU core and the bus in response to said at least one bus clock signal while the CPU core and the bus controller operate at the clock speed of said at least one core clock signal; wherein the clock generator comprises a phase locked loop comprising a phase detector to receive an external clock signal and a feedback signal and to generate a first signal in response thereto that is a measure of on phase difference between the external clock signal and the feedback signal; a voltage generator to generate a voltage control signal in accordance with the first signal; a voltage-controlled oscillator to generate said at least one core clock signal in response to the voltage control signal; and a frequency divider to generate the feedback signal in response to said at least one core clock signal, said feedback signal having a frequency which is a multiple of said at least one core clock signal, such that the oscillator produces a signal which is N times the frequency of the external clock signal.
Claim 18
Dependent Claim
86 words
The processor defined by claim 13 wherein the frequency divider comprises: a first logic to generate a masking signal in response to one of said at least one core clock signal, said masking signal being at a first state or a second state; and a second logic to generate the feedback signal in response to said one core clock signal and the masking signal when the masking signal is in the first state and masks the feedback signal the masking signal is in the second state.
Claim 19
Dependent Claim
102 words
An integrated circuit for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said integrated circuit comprising: a core to perform operations in response to said at least one core clock signal having a frequency greater than the first frequency; and a bus controller coupled to the core and the bus to transfer data between the core and the bus in accordance with said at least one bus clock signal while the core and the bus controller operate at the clock speed of said at least one core clock signal.
Claim 20
Dependent Claim
102 words
An integrated circuit for use in a computer system having a bus operating according to at least one bus clock signal at a first frequency, said integrated circuit comprising: a core to perform operations in response to said at least one core clock signal having a frequency greater than the first frequency; and a bus controller coupled to the core and the bus to transfer data between the core and the bus in accordance with said at least one bus clock signal while the core and the bus controller operate at the clock speed of said at least one core clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-15 | 2002-09-14 | 2003-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-15 | 2006-09-14 | 2007-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-15 | 2010-09-14 | 2011-03-16 | $7700.00 | Window Closed / Lapsed |