Patent US5883433A successfully refreshed from Google Patents.
US5883433A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having a critical path wiring
Assignee: NEC Electronics Corp
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Filing: 1996-04-24
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Granted: 1999-03-16
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Expires: 2016-04-24
Abstract
Abstract Disclosed is a semiconductor device, which has: a wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuity, and a wiring corresponding to other than the critical path. The critical path wiring the other wiring are formed on the same wiring layer, wherein a thickness of at least a part of the critical path wiring is greater than that of the other wiring.
Inventors
- 👤 Noriaki Oda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:36
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/40; H10W20/495; H10W20/41; H10W20/425; H10W20/435
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
166 words
A semiconductor device having at least one wiring layer, comprising: a critical path wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuit, formed on said at least one wiring layer; and other path wiring corresponding to other than said critical path wiring said other path wiring formed on said at least one wiring layer, wherein a thickness of at least a part of said critical path wiring in said at least one wiring layer is greater than that of said other wiring in said at least one wiring layer; an upper wiring layer formed to overlap said critical path wiring and said other path wiring; at least one via-hole formed between said upper wiring layer and said lower wiring layer, including said critical path wiring and said other path wiring, such that said upper wiring layer and said lower wiring layer are electrically connected by a conductive material buried in said at least one via-hole.
Claim 2
Dependent Claim
166 words
A semiconductor device having at least one wiring layer, comprising: a critical path wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuit, formed on said at least one wiring layer; and other path wiring corresponding to other than said critical path wiring said other path wiring formed on said at least one wiring layer, wherein a thickness of at least a part of said critical path wiring in said at least one wiring layer is greater than that of said other wiring in said at least one wiring layer; an upper wiring layer formed to overlap said critical path wiring and said other path wiring; at least one via-hole formed between said upper wiring layer and said lower wiring layer, including said critical path wiring and said other path wiring, such that said upper wiring layer and said lower wiring layer are electrically connected by a conductive material buried in said at least one via-hole.
Claim 3
Dependent Claim
33 words
A semiconductor device, according to claim 1, wherein: said critical path wiring comprises a first layer and a second layer formed on said first layer; and said other wiring comprises said first layer.
Claim 4
Dependent Claim
22 words
A semiconductor device, according to claim 2, wherein: said first layer is made of the same conductive material as said second layer.
Claim 5
Dependent Claim
22 words
A semiconductor device, according to claim 2, wherein: said first layer is made of a conductive material different from said second layer.
Claim 6
Dependent Claim
79 words
A semiconductor device, according to claim 2, further comprising: an upper wiring layer formed to overlap said critical path wiring and said other path wiring; and at least one via-hole formed between said upper wiring layer and said at least one wiring layer including said critical path wiring and said other path wiring; wherein said upper wiring layer and said at least one wiring layer are electrically connected by a conductive material buried in said at least one via-hole.
Claim 7
Dependent Claim
34 words
A semiconductor device, according to claim 1, wherein: said buried conductive material is composed of a part of said upper wiring layer which is formed to be buried into said at least one via-hole.
Claim 8
Dependent Claim
34 words
A semiconductor device, according to claim 5, wherein: said buried conductive material is composed of a part of said upper wiring layer which is formed to be buried into said at least one via-hole.
Claim 9
Dependent Claim
140 words
A semiconductor device, comprising: a critical path wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuit, said critical path wiring formed in a lower wiring layer; other path wiring corresponding to other than said critical path, formed in said lower wiring layer, having a thickness such that said critical path wiring is thicker than said other path wiring in said lower wiring layer; an upper wiring layer formed to overlap said critical path wiring and said other path wiring; at least one via-hole formed between said upper wiring layer and said lower wiring layer, including said critical path wiring and said other path wiring, such that said upper wiring layer and said lower wiring layer are electrically connected by a conductive material buried in said at least one via-hole.
Claim 10
Dependent Claim
140 words
A semiconductor device, comprising: a critical path wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuit, said critical path wiring formed in a lower wiring layer; other path wiring corresponding to other than said critical path, formed in said lower wiring layer, having a thickness such that said critical path wiring is thicker than said other path wiring in said lower wiring layer; an upper wiring layer formed to overlap said critical path wiring and said other path wiring; at least one via-hole formed between said upper wiring layer and said lower wiring layer, including said critical path wiring and said other path wiring, such that said upper wiring layer and said lower wiring layer are electrically connected by a conductive material buried in said at least one via-hole.
Claim 11
Dependent Claim
124 words
A semiconductor device having at least one wiring layer, comprising: a critical path wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuit, formed on said at least one wiring layer; and other path wiring corresponding to other than said critical path wiring said other path wiring formed on said at least one wiring layer; wherein a thickness of at least a part of said critical path wiring in said at least one wiring layer is greater than that of said other wiring in said at least one wiring layer and where said at least one wiring layer makes electrical contact through a contact hole in an underlying insulating layer to a semiconductor substrate.
Claim 12
Dependent Claim
124 words
A semiconductor device having at least one wiring layer, comprising: a critical path wiring corresponding to a critical path, a wiring delay time of which determines an operating speed of an entire circuit, formed on said at least one wiring layer; and other path wiring corresponding to other than said critical path wiring said other path wiring formed on said at least one wiring layer; wherein a thickness of at least a part of said critical path wiring in said at least one wiring layer is greater than that of said other wiring in said at least one wiring layer and where said at least one wiring layer makes electrical contact through a contact hole in an underlying insulating layer to a semiconductor substrate.
Claim 13
Dependent Claim
33 words
A semiconductor device, according to claim 1, wherein: said critical path wiring comprises a first layer and a second layer formed on said first layer; and said other wiring comprises said first layer.
Claim 14
Dependent Claim
22 words
A semiconductor device, according to claim 2, wherein: said first layer is made of the same conductive material as said first layer.
Claim 15
Dependent Claim
22 words
A semiconductor device, according to claim 2, wherein: said first layer is made of a conductive material different from said first layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-15 | 2002-09-14 | 2003-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-15 | 2006-09-14 | 2007-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-15 | 2010-09-14 | 2011-03-16 | $7700.00 | Window Closed / Lapsed |