US5812488A
Expired / Lapsed
US
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Synchronous burst extended data out dram
Assignee: Round Rock Research LLC
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Filing: 1997-03-05
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Granted: 1998-09-22
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Expires: 2017-03-05
Abstract
Abstract An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. A clock signal is provided to synchronize the burst operations. The clock signal is independent of an address latch signal used to latch an external address.
Inventors
- 👤 Paul S. Zagar
- 👤 Troy A. Manning
- 👤 Todd Merritt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:51
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/109; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/1024; G11C7/1039; G11C7/1045; G11C7/1072; G11C7/1096; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
99 words
A memory device comprising: a plurality of addressable memory elements; addressing circuitry adapted to receive a first memory element address in response to a transition of a clock signal and an address latch signal, and further adapted to generate a second memory element address in response to a subsequent transition of the clock signal, wherein the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.
Claim 2
Dependent Claim
99 words
A memory device comprising: a plurality of addressable memory elements; addressing circuitry adapted to receive a first memory element address in response to a transition of a clock signal and an address latch signal, and further adapted to generate a second memory element address in response to a subsequent transition of the clock signal, wherein the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.
Claim 3
Dependent Claim
128 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses, the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.
Claim 4
Dependent Claim
128 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses, the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.
Claim 5
Independent Claim
106 words
A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal, wherein the first memory element address is received in response to a rising transition of the clock signal when the address latch signal is at a low voltage level; receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
Claim 6
Independent Claim
106 words
A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal, wherein the first memory element address is received in response to a rising transition of the clock signal when the address latch signal is at a low voltage level; receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
Claim 7
Independent Claim
97 words
A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal; accessing additional memory elements having the additional memory element addresses; receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
Claim 8
Independent Claim
97 words
A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal; accessing additional memory elements having the additional memory element addresses; receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
Claim 9
Independent Claim
129 words
A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal; accessing additional memory elements having the additional memory element addresses; synchronously reading a memory array row address in response to an active row access signal (RAS\); synchronously reading a memory array column address in response to an active column access signal (CAS\); receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
Claim 10
Independent Claim
129 words
A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal; accessing additional memory elements having the additional memory element addresses; synchronously reading a memory array row address in response to an active row access signal (RAS\); synchronously reading a memory array column address in response to an active column access signal (CAS\); receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
Claim 11
Dependent Claim
135 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; and an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state, the address generation circuit including a counter circuit coupled to the address latch to enable the address latch to receive a new address from the plurality of address inputs after a predetermined number of access cycles.
Claim 12
Dependent Claim
135 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; and an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state, the address generation circuit including a counter circuit coupled to the address latch to enable the address latch to receive a new address from the plurality of address inputs after a predetermined number of access cycles.
Claim 13
Dependent Claim
121 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and the first memory element address is received on a rising edge of the clock signal when the address latch signal is low.
Claim 14
Dependent Claim
121 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and the first memory element address is received on a rising edge of the clock signal when the address latch signal is low.
Claim 15
Dependent Claim
113 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and the additional memory element addresses are generated on rising edges of the clock signal.
Claim 16
Dependent Claim
113 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and the additional memory element addresses are generated on rising edges of the clock signal.
Claim 17
Dependent Claim
130 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and an output buffer circuit adapted to drive data from the synchronous memory device, and further adapted to switch between data values in response to a falling transition of the clock signal.
Claim 18
Dependent Claim
130 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and an output buffer circuit adapted to drive data from the synchronous memory device, and further adapted to switch between data values in response to a falling transition of the clock signal.
Claim 19
Dependent Claim
134 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and a write enable input for receiving a write enable signal, and adapted to switch between read and write access cycles of the synchronous memory device and to terminate a burst access of the memory array.
Claim 20
Dependent Claim
134 words
A synchronous memory device comprising: a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and a write enable input for receiving a write enable signal, and adapted to switch between read and write access cycles of the synchronous memory device and to terminate a burst access of the memory array.
Claim 21
Independent Claim
99 words
A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal and while the address latch signal is in an inactive state, wherein the first memory element address is received in response to a rising transition of the clock signal when the address latch signal is at a low voltage level.
Claim 22
Independent Claim
99 words
A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal and while the address latch signal is in an inactive state, wherein the first memory element address is received in response to a rising transition of the clock signal when the address latch signal is at a low voltage level.
Claim 23
Independent Claim
69 words
A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal while the address latch signal is in an inactive state.
Claim 24
Independent Claim
69 words
A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal while the address latch signal is in an inactive state.
Claim 25
Dependent Claim
24 words
The method of claim 12 further wherein the additional memory element addresses are generated in response to subsequent rising edges of the clock signal.
Claim 26
Dependent Claim
27 words
The method of claim 12 further including the step of: outputting data stored at the first and additional memory element addresses in response to the clock signal.
Claim 27
Dependent Claim
26 words
The method of claim 12 further including the step of: storing data at the first and additional memory element addresses in response to the clock signal.
Claim 28
Independent Claim
90 words
A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal while the address latch signal is in an inactive state; and accessing additional memory elements having the additional memory element addresses.
Claim 29
Independent Claim
90 words
A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of: receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal while the address latch signal is in an inactive state; and accessing additional memory elements having the additional memory element addresses.
Claim 30
Dependent Claim
25 words
The method of claim 16 further comprising the steps of: storing data at the first memory elements; and storing data at the additional memory elements.
Claim 31
Dependent Claim
28 words
The method of claim 16 further comprising the steps of: reading data stored at the first memory elements; and reading data stored data at the additional memory elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-21 | 2002-03-23 | 2002-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-21 | 2006-03-23 | 2006-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-21 | 2010-03-23 | 2010-09-22 | $7700.00 | Window Closed / Lapsed |