US5452261A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial address generator for burst memory
Assignee: HOME SEMICONDUCTOR Corp
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Filing: 1994-06-24
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Granted: 1995-09-19
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Expires: 2014-06-24
Abstract
Abstract A serial address generator for a sequential (burst mode) random access memory generates a sequence of internally generated addresses for fast cycling. The start address is externally provided. Then, as the clock signals arrive, the subsequent addresses are generated in sequence by the address sequencer. The address sequencer is preset to the second address in the sequence following the start address. Simultaneously, the start address is connected by an external address enable switch to an output terminal of the address generator, bypassing the address sequencer. When the first clock signal arrives at the address sequencer, the address sequencer output is sampled by closing an internal address enable switch and opening the external address enable switch. Thus the internally generated addresses are provided immediately following the start address. The address sequencer thereby generates each address one clock cycle ahead of that in the prior art, and the output address is provided one half clock cycle ahead of that in the prior art.
Inventors
- 👤 Jinyong Chung
- 👤 Michael A. Murray
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:47
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
113 words
An address generator for a random access memory, comprising: an address sequencer having a clock input terminal, a preset terminal, and an output terminal; an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; and an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; wherein the address sequencer includes means for incrementally timing the address sequencer to generate a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.
Claim 2
Dependent Claim
113 words
An address generator for a random access memory, comprising: an address sequencer having a clock input terminal, a preset terminal, and an output terminal; an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; and an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; wherein the address sequencer includes means for incrementally timing the address sequencer to generate a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.
Claim 3
Dependent Claim
77 words
The address generator of claim 1, further comprising: means for controlling the internal address enable switch; and means for controlling the external address enable switch, wherein the means for controlling the external address enable switch closes the external address enable switch for a duration of the first address of the sequence of addresses, and wherein during the duration the external address enable switch is closed, the address sequencer generates the second address in the sequence of addresses.
Claim 4
Dependent Claim
29 words
The address generator of claim 1, wherein the second address is output to the output terminal of the address sequencer only when the internal address enable switch is closed.
Claim 5
Dependent Claim
28 words
The address generator of claim 1, further comprising a buffer serially connected between the output terminal of the address sequencer and the output terminal of the address generator.
Claim 6
Dependent Claim
52 words
The address generator of claim 2, further comprising means for providing a preset signal of a predetermined duration and level to the preset terminal during at least a portion of the duration of the first address, the preset signal setting the address sequencer to the second address in the sequence of addresses.
Claim 7
Dependent Claim
36 words
The address generator of claim 2, further comprising means for providing clock signals of predetermined level to the clock input terminal, a first of the clock signals occurring only after the duration of the first address.
Claim 8
Dependent Claim
21 words
The address generator of claim 2, wherein the address sequencer includes a counter having a master portion and a slave portion.
Claim 9
Dependent Claim
37 words
The address generator of claim 1, further comprising means for providing an externally generated address to the address input terminal, wherein the externally generated address is a first address of a page of the random access memory.
Claim 10
Dependent Claim
143 words
An address generator for a random access memory, comprising: means for providing a first address in a sequence of addresses, the first address being provided from an external source as an output address; an address sequencer for generating the subsequent addresses in the sequence of addresses, a second address in the sequence being provided as an output address immediately following the generation of the first address; an internal address enable switch connected between an output terminal of the address sequencer and an output terminal of the address generator; an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and means for incrementally timing the address sequencer during a preset period to generate the second address at a same time that the first address is being provided from the external source.
Claim 11
Dependent Claim
143 words
An address generator for a random access memory, comprising: means for providing a first address in a sequence of addresses, the first address being provided from an external source as an output address; an address sequencer for generating the subsequent addresses in the sequence of addresses, a second address in the sequence being provided as an output address immediately following the generation of the first address; an internal address enable switch connected between an output terminal of the address sequencer and an output terminal of the address generator; an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and means for incrementally timing the address sequencer during a preset period to generate the second address at a same time that the first address is being provided from the external source.
Claim 12
Independent Claim
100 words
A method of generating a sequence of addresses for addressing a random access memory, comprising the steps of: providing from an external source a first address in the sequence as an output address; switching in the first address as an output address during a preset period; then, providing from an address sequencer a second address in the sequence as an output address, the second address being generated by incremental timing during at least a part of a duration of the step of providing the first address; and switching in the second address as an output address after the preset period.
Claim 13
Independent Claim
100 words
A method of generating a sequence of addresses for addressing a random access memory, comprising the steps of: providing from an external source a first address in the sequence as an output address; switching in the first address as an output address during a preset period; then, providing from an address sequencer a second address in the sequence as an output address, the second address being generated by incremental timing during at least a part of a duration of the step of providing the first address; and switching in the second address as an output address after the preset period.
Claim 14
Dependent Claim
29 words
The address generator of claim 2, wherein the means for controlling the internal address enable switch is a logical inversion of the signals provided to the clock input terminal.
Claim 15
Dependent Claim
146 words
An address generator for a random access memory, comprising: an address sequencer having a clock input terminal, a preset terminal, and an output terminal; an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and means for providing a preset signal of a predetermined duration and level to the preset terminal during at least a portion of the duration of the first address, the preset signal setting the address sequencer to the second address in the series; wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.
Claim 16
Dependent Claim
146 words
An address generator for a random access memory, comprising: an address sequencer having a clock input terminal, a preset terminal, and an output terminal; an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and means for providing a preset signal of a predetermined duration and level to the preset terminal during at least a portion of the duration of the first address, the preset signal setting the address sequencer to the second address in the series; wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.
Claim 17
Dependent Claim
132 words
An address generator for a random access memory, comprising: an address sequencer having a clock input terminal, a preset terminal, and an output terminal; an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and means for providing clock signals of predetermined level to the clock input terminal, a first of the clock signals occurring only after the duration of the first address; wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.
Claim 18
Dependent Claim
132 words
An address generator for a random access memory, comprising: an address sequencer having a clock input terminal, a preset terminal, and an output terminal; an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; and means for providing clock signals of predetermined level to the clock input terminal, a first of the clock signals occurring only after the duration of the first address; wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch.
Claim 19
Dependent Claim
120 words
An address generator for a random access memory, comprising: an address sequencer having a clock input terminal, a preset terminal, and an output terminal; an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; and an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch, and wherein the address sequencer includes a counter having a master portion and a slave portion.
Claim 20
Dependent Claim
120 words
An address generator for a random access memory, comprising: an address sequencer having a clock input terminal, a preset terminal, and an output terminal; an internal address enable switch connected between the output terminal of the address sequencer and an output terminal of the address generator; and an external address enable switch connected between an address input terminal of the address generator and the output terminal of the address generator; wherein the address sequencer generates a second address in a sequence of addresses while a first address is being supplied to the output terminal of the address generator by the external address enable switch, and wherein the address sequencer includes a counter having a master portion and a slave portion.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |