US5146431A
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US
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Method and apparatus for page recall of data in an nonvolatile DRAM memory device
Assignee: Sharp Corp
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Filing: 1990-09-20
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Granted: 1992-09-08
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Expires: 2010-09-20
Abstract
Abstract In a non-volatile DRAM (NVDRAM) memory device comprised of NVDRAM cells, each comprising a DRAM cell and an EEPROM cell, a method and apparatus for the page recall of data whereby the page recall start address may be specified by the user through the memory device's external control pins. A page of memory cells is defined as all of the memory cells connected to a single word line. During any recall operation, data are recalled from EEPROM to DRAM in only one memory cell per bit line. The externally specified page recall start address is input onto an external pad. It is then transmitted through an address selector circuit into the inputs of a counter circuit. The outputs of the counter circuit serve as the page recall start address, which reenters the address selector circuitry to be transmitted to address decoding circuitry.
Inventors
- 👤 Michael D. Eby
- 👤 Katsumi Fukumoto
- 👤 Michael J. Griffus
- 👤 Giao N. Pham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:48
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
224 words
In an NVDRAM memory device having address lines, an apparatus for the page recall of data, comprising: an external pad connected to the address lines for inputting a predetermined page recall start address comprising a plurality of first start address signals, wherein said external pad includes a plurality of external pad outputs, with each said external pad output for outputting one said first start address signal; a plurality of address selector circuits, wherein one said address selector circuit is connected to each said external pad output, each said address selector circuit having a first address selector output for outputting a second start address signal corresponding to one said first start address signal; a counter circuit having a plurality of counter inputs, each said counter input being connected to one said first address selector output for receiving one of said second start address signals, said counter circuit further including a plurality of counter outputs, wherein each said address selector circuit includes an address selector input, and wherein each said counter output is connected to one said address selector input, wherein each said address selector circuit has a second address selector output corresponding to one of said first start address signals; and address decoding circuitry having as address decoding inputs said second address selector outputs, said address decoding circuitry for addressing a page of said data.
Claim 2
Dependent Claim
224 words
In an NVDRAM memory device having address lines, an apparatus for the page recall of data, comprising: an external pad connected to the address lines for inputting a predetermined page recall start address comprising a plurality of first start address signals, wherein said external pad includes a plurality of external pad outputs, with each said external pad output for outputting one said first start address signal; a plurality of address selector circuits, wherein one said address selector circuit is connected to each said external pad output, each said address selector circuit having a first address selector output for outputting a second start address signal corresponding to one said first start address signal; a counter circuit having a plurality of counter inputs, each said counter input being connected to one said first address selector output for receiving one of said second start address signals, said counter circuit further including a plurality of counter outputs, wherein each said address selector circuit includes an address selector input, and wherein each said counter output is connected to one said address selector input, wherein each said address selector circuit has a second address selector output corresponding to one of said first start address signals; and address decoding circuitry having as address decoding inputs said second address selector outputs, said address decoding circuitry for addressing a page of said data.
Claim 3
Dependent Claim
115 words
The apparatus of claim 1, wherein each said address selector circuit comprises: a first NAND gate having as an input one of said external pad outputs and an address enable signal, and having a NAND gate output; a first transmission gate having as an input said NAND gate output, and having a first transmission gate output; a second transmission gate having as an input one of said counter output, and having a second transmission gate output; and wherein said first transmission gate and said second transmission gate outputs are coupled together for providing one of said first transmission gate output and said second transmission gate output at a time as said first address selector output.
Claim 4
Dependent Claim
12 words
The apparatus of claim 1, including means for incrementing said counter outputs.
Claim 5
Dependent Claim
24 words
An apparatus according to claim 3, wherein said apparatus recalls consecutive pages of data as a function of said incrementing of said counter outputs.
Claim 6
Independent Claim
242 words
A method for page recall of data in an array of NVDRAM memory cells, wherein the array includes a plurality of bit lines, a plurality of word lines and a plurality of recall lines; wherein one bit line, one word line and one recall line is connected to each of the cells; where each bit line is connected to one of a plurality of first subset of cells in the array of cells which does not overlap with others of said first subsets of the cells to which other bit lines are connected; and where one word line and a corresponding recall line are connected to each of a plurality of second subsets of cells in the array of cells which does not overlap with others of said second subsets of the cells to which other word lines and bit lines are connected; including the steps of: (1) activating a single one of the plurality of word lines, for addressing each cell of the second subset of cells to which the activated word line is connected, thus creating an activated second subset of cells; (2) activating all of the bit lines, for accessing each cell in any of the first subsets of cells which is also in the activated second subset of cells; and (3) activating a recall line associated with the activated word line, for recalling data from each of the cells which is accessed as a result of step 2.
Claim 7
Independent Claim
242 words
A method for page recall of data in an array of NVDRAM memory cells, wherein the array includes a plurality of bit lines, a plurality of word lines and a plurality of recall lines; wherein one bit line, one word line and one recall line is connected to each of the cells; where each bit line is connected to one of a plurality of first subset of cells in the array of cells which does not overlap with others of said first subsets of the cells to which other bit lines are connected; and where one word line and a corresponding recall line are connected to each of a plurality of second subsets of cells in the array of cells which does not overlap with others of said second subsets of the cells to which other word lines and bit lines are connected; including the steps of: (1) activating a single one of the plurality of word lines, for addressing each cell of the second subset of cells to which the activated word line is connected, thus creating an activated second subset of cells; (2) activating all of the bit lines, for accessing each cell in any of the first subsets of cells which is also in the activated second subset of cells; and (3) activating a recall line associated with the activated word line, for recalling data from each of the cells which is accessed as a result of step 2.
Claim 8
Dependent Claim
94 words
An NVDRAM memory device having a plurality of NVDRAM cells, each NVDRAM cell including a DRAM cell and a corresponding EEPROM cell, said NVDRAM memory device comprising: means for reading and writing data to said DRAM cells; store mode means for transferring data in said DRAM cells to said corresponding EEPROM cells; and recall mode means for transferring data in said corresponding EEPROM cells to said DRAM cells, wherein said recall mode means comprises means for simultaneously transferring data in a plurality of said corresponding EEPROM cells to a plurality of said DRAM cells.
Claim 9
Dependent Claim
94 words
An NVDRAM memory device having a plurality of NVDRAM cells, each NVDRAM cell including a DRAM cell and a corresponding EEPROM cell, said NVDRAM memory device comprising: means for reading and writing data to said DRAM cells; store mode means for transferring data in said DRAM cells to said corresponding EEPROM cells; and recall mode means for transferring data in said corresponding EEPROM cells to said DRAM cells, wherein said recall mode means comprises means for simultaneously transferring data in a plurality of said corresponding EEPROM cells to a plurality of said DRAM cells.
Claim 10
Dependent Claim
72 words
The memory device of claim 6, further comprising a plurality of bit lines and a plurality of word lines, one bit line and one word line being connected to each of said NVDRAM cells and each of said word lines being connected to a plurality of said NVDRAM cells, and wherein said plurality of said corresponding EEPROM cells and said plurality of said DRAM cells are associated with a common word line.
Claim 11
Dependent Claim
20 words
The memory device of claim 7, further comprising address input means for inputting an address of said common word line.
Claim 12
Dependent Claim
26 words
The memory device of claim 8, further comprising counter means for generating a plurality of addresses utilized consecutively as said address of said common word line.
References Cited (Backward Citations)
US4471471A
Cited
US4611309A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-08 | 1996-03-09 | 1996-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-08 | 2000-03-09 | 2000-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-08 | 2004-03-09 | 2004-09-08 | $7700.00 | Window Closed / Lapsed |