US5386385A
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Method and apparatus for preventing invalid operating modes and an application to synchronous memory devices
Assignee: Texas Instruments Inc
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Filing: 1994-01-31
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Granted: 1995-01-31
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Expires: 2014-01-31
Abstract
Abstract A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns in each of the memory sections (respectively, 32, 36, 30 and 34). The column decoders (58, 60, 62, and 64) decode addresses received from counters (respectively 52, 54, 48, and 50), an adder (46), and a latch (56). Counters (48, 50, 52, and 54) and adder (46) generate column addresses for each memory section based on a starting address, thereby allowing for internal operation at less than the external system frequency. An operation mode register (29) stores mode data for controlling certain operations, and a state machine (130) operates to prevent indeterminate operation if invalid mode data is input to the operation mode register (29).
Inventors
- 👤 Michael C. Stephens, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:31
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
163 words
A synchronous memory device for storing data, comprising: a timing and control circuit operable to receive address and control inputs and to generate internal control signals, one of said control inputs comprising a system clock operating at a system frequency; a memory bank including a plurality of memory sections, each of said memory sections including an array of memory cells arranged in rows and columns; a row decoder coupled to said timing and control circuit and operable to enable rows in each of said memory sections; a column decoder coupled to said timing and control circuit and operable to synchronously enable columns in each of said memory sections substantially simultaneously; an operation mode register operable to store mode data corresponding to operating modes for the memory device; and a state machine coupled to the operation mode register and operable to decode the mode data such that mode data corresponding to invalid operating modes is prevented from causing indeterminate operation of the memory device.
Claim 2
Dependent Claim
163 words
A synchronous memory device for storing data, comprising: a timing and control circuit operable to receive address and control inputs and to generate internal control signals, one of said control inputs comprising a system clock operating at a system frequency; a memory bank including a plurality of memory sections, each of said memory sections including an array of memory cells arranged in rows and columns; a row decoder coupled to said timing and control circuit and operable to enable rows in each of said memory sections; a column decoder coupled to said timing and control circuit and operable to synchronously enable columns in each of said memory sections substantially simultaneously; an operation mode register operable to store mode data corresponding to operating modes for the memory device; and a state machine coupled to the operation mode register and operable to decode the mode data such that mode data corresponding to invalid operating modes is prevented from causing indeterminate operation of the memory device.
Claim 3
Dependent Claim
21 words
The synchronous memory of device of claim 1, wherein said memory bank comprises an array of dynamic random access memory cells.
Claim 4
Dependent Claim
15 words
The synchronous memory device of claim 1, wherein said memory bank includes two memory sections.
Claim 5
Dependent Claim
79 words
The synchronous memory device of claim 1, wherein said state machine comprises: a burst length state machine operable to decode burst length data stored in said operation mode register such that invalid burst length data is prevented from causing indeterminate operation of the memory device; and a read latency state machine operable to decode read latency data stored in said operation mode register such that invalid read latency data is prevented from causing indeterminate operation of the memory device.
Claim 6
Dependent Claim
21 words
The synchronous memory device of claim 1, wherein said mode data transmitted to said operation mode register across an address bus.
Claim 7
Dependent Claim
76 words
The synchronous memory device of claim 1, wherein said state machine comprises: an input decoder coupled to said operation mode register; a valid state latch coupled to said input decoder, said input decoder operable to cause decoded data to be latched by said valid state latch when mode data corresponding to valid operating modes is stored in said operation mode register; and an output decoder circuit operable to decode data latched in said valid state latch.
Claim 8
Dependent Claim
42 words
The synchronous memory device of claim 6, wherein: said valid state latch comprises a plurality of flip-flops; and said input decoder prevents said flip-flops from changing states when mode data corresponding to invalid operating modes is stored in said operation mode register.
Claim 9
Dependent Claim
39 words
The synchronous memory device of claim 6, and further comprising reset circuitry operable to reset said operation mode register to a known valid state when mode data corresponding to invalid operating modes is stored in said operation mode register.
Claim 10
Dependent Claim
34 words
The synchronous memory device of claim 6, and further comprising error message circuitry operable to generate an error message when mode data corresponding to invalid operating modes is stored in said operation mode register.
Claim 11
Dependent Claim
84 words
A circuit for preventing indeterminate operation of a device, comprising: a mode register operable to store mode data for controlling the device; an input decoder coupled to said mode register; a valid state latch coupled to said input decoder, said input decoder operable to cause decoded data to be latched by said valid state latch when mode data corresponding to valid operating modes is stored in said mode register; and an output decoder circuit operable to decode data latched in said valid state latch.
Claim 12
Dependent Claim
84 words
A circuit for preventing indeterminate operation of a device, comprising: a mode register operable to store mode data for controlling the device; an input decoder coupled to said mode register; a valid state latch coupled to said input decoder, said input decoder operable to cause decoded data to be latched by said valid state latch when mode data corresponding to valid operating modes is stored in said mode register; and an output decoder circuit operable to decode data latched in said valid state latch.
Claim 13
Dependent Claim
39 words
The circuit of claim 10, wherein: said valid state latch comprises a plurality of flip-flops; and said input decoder prevents said flip-flops from changing states when mode data corresponding to invalid operating modes is stored in said mode register.
Claim 14
Dependent Claim
34 words
The circuit of claim 10, and further comprising reset circuitry operable to reset said mode register to a known valid state when mode data corresponding to invalid states is stored in said mode register.
Claim 15
Dependent Claim
30 words
The circuit of claim 10, and further comprising error message circuitry operable to generate an error message when mode data corresponding to invalid states is stored in said mode register.
Claim 16
Independent Claim
113 words
A method of preventing indeterminate operation of a synchronous memory device, comprising the steps of: receiving address and control inputs, one of the control inputs comprising a system clock operating at a system frequency; in response to the address and control inputs, enabling predetermined rows in a plurality of memory sections; in response to the address and control inputs, synchronously enabling predetermined columns in each of the plurality of memory sections substantially simultaneously; storing mode data corresponding to operating modes for the memory device in an operation mode register; and decoding the mode data such that mode data corresponding to invalid operating modes is prevented from causing indeterminate operation of the memory device.
Claim 17
Independent Claim
113 words
A method of preventing indeterminate operation of a synchronous memory device, comprising the steps of: receiving address and control inputs, one of the control inputs comprising a system clock operating at a system frequency; in response to the address and control inputs, enabling predetermined rows in a plurality of memory sections; in response to the address and control inputs, synchronously enabling predetermined columns in each of the plurality of memory sections substantially simultaneously; storing mode data corresponding to operating modes for the memory device in an operation mode register; and decoding the mode data such that mode data corresponding to invalid operating modes is prevented from causing indeterminate operation of the memory device.
Claim 18
Dependent Claim
65 words
The method of claim 14, wherein said step of decoding data comprises: decoding burst length data stored in the operation mode register such that invalid burst length data is prevented from causing indeterminate operation of the memory device; and decoding read latency data stored in the operation mode register such that invalid read latency data is prevented from causing indeterminate operation of the memory device.
Claim 19
Dependent Claim
50 words
The method of claim 14, wherein said step of decoding data comprises: decoding the mode data stored in the operation mode register; latching decoded data when mode data corresponding to valid operating modes is stored in the operation mode register; and decoding latched data for control of the memory device.
Claim 20
Dependent Claim
37 words
The method of claim 16, wherein said step of decoding the mode data comprises preventing a plurality of flip-flops from changing states when mode data corresponding to invalid operating modes is stored in the operation mode register.
Claim 21
Dependent Claim
36 words
The method of claim 16, and further comprising the step of resetting the operation mode register to a known valid state when mode data corresponding to invalid operating modes is stored in the operation mode register.
Claim 22
Dependent Claim
30 words
The method of claim 16, and further comprising the step of generating an error message when mode data corresponding to invalid operating modes is stored in the operation mode register.
Claim 23
Independent Claim
59 words
A method of preventing indeterminate operation of a device, comprising the steps of: storing mode data for controlling the device in a mode register; decoding the mode data stored in the mode register; latching decoded data when mode data corresponding to valid operating modes is stored in the mode register; and decoding latched data for control of the device.
Claim 24
Independent Claim
59 words
A method of preventing indeterminate operation of a device, comprising the steps of: storing mode data for controlling the device in a mode register; decoding the mode data stored in the mode register; latching decoded data when mode data corresponding to valid operating modes is stored in the mode register; and decoding latched data for control of the device.
Claim 25
Dependent Claim
36 words
The method of claim 20, wherein said step of decoding the mode data comprises preventing a plurality of flip-flops from changing states when mode data corresponding to invalid operating modes is stored in the mode register.
Claim 26
Dependent Claim
34 words
The method of claim 2, and further comprising the step of resetting the mode register to a known valid state when mode data corresponding to invalid operating modes is stored in the mode register.
Claim 27
Dependent Claim
29 words
The method of claim 20, and further comprising the step of generating an error message when mode data corresponding to invalid operating modes is stored in the mode register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-30 | 1998-08-01 | 1999-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-30 | 2002-08-01 | 2003-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-30 | 2006-08-01 | 2007-01-31 | $7700.00 | Window Closed / Lapsed |