US5058066A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output buffer precharge circuit for DRAM
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-02-27
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Granted: 1991-10-15
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Expires: 2010-02-27
Abstract
Abstract An output buffer precharge circuit for DRAM (dynamic random access memory) cells includes a latch, control circuits, an output buffer, and a precharge pulse generating section. The circuit further includes a data transition signal genrating section consisting of MOS (metal-oxide semiconductor) transistors, latches connected to the MOS transistors, inverters and NAND gates for receiving the control precharge pulse from the precharge pulse generating section; and a precharge section consisting of MOS transistors, the gates of which receive the outputs of the data transition signal generating section. Noise can be decreased during the transition from the CMOS level to the TTL (transistor-transition-logic) level, and valid data are charged or discharged in advance so that processing speed can be increased.
Inventors
- 👤 Jaiwhan Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 10:06
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/106; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C11/4093; G11C11/4096; G11C7/1048
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
213 words
An output buffer precharge circuit for dynamic random access memory (DRAM) cells, including an output buffer 5 having a latch 1; control circuits 2, 3 for outputting data after receipt of outputs of said latch 1 and a control signal .0.TRST; MOS transistors driven by outputs of said control circuits 2, 3; a precharge pulse generating section 10 for outputting control precharge pulses DCPP in response to address transition signals ATS; and a precharge section 9 for receiving outputs DOUT of said output buffer 5; characterized in that said output buffer precharge circuit further comprises a data transition signal generating section 15 comprising: MOS transistors M7, M8 for receiving said control signal .0.TRST at respective gates thereon and for selectively transmitting data signals DB, DB as data signals D1P, D.0.P respectively to be supplied to said precharge section 9; latches 11, 12 connected to said MOS transistors M7, M8; NAND gates ND1, ND2 for receiving said control precharge pulse DCPP from said precharge pulse generating section 10, and inverters I7, I8, outputs of said NAND gates being respectively connected to inputs of said inverters; and wherein said precharge section 9 comprises MOS transistors M5, M6, the gates of which respectively receive said data signals D.0.P, D1P from said transition signal generating section 15.
Claim 2
Dependent Claim
213 words
An output buffer precharge circuit for dynamic random access memory (DRAM) cells, including an output buffer 5 having a latch 1; control circuits 2, 3 for outputting data after receipt of outputs of said latch 1 and a control signal .0.TRST; MOS transistors driven by outputs of said control circuits 2, 3; a precharge pulse generating section 10 for outputting control precharge pulses DCPP in response to address transition signals ATS; and a precharge section 9 for receiving outputs DOUT of said output buffer 5; characterized in that said output buffer precharge circuit further comprises a data transition signal generating section 15 comprising: MOS transistors M7, M8 for receiving said control signal .0.TRST at respective gates thereon and for selectively transmitting data signals DB, DB as data signals D1P, D.0.P respectively to be supplied to said precharge section 9; latches 11, 12 connected to said MOS transistors M7, M8; NAND gates ND1, ND2 for receiving said control precharge pulse DCPP from said precharge pulse generating section 10, and inverters I7, I8, outputs of said NAND gates being respectively connected to inputs of said inverters; and wherein said precharge section 9 comprises MOS transistors M5, M6, the gates of which respectively receive said data signals D.0.P, D1P from said transition signal generating section 15.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-10-14 | 1995-04-15 | 1995-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-10-14 | 1999-04-15 | 1999-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-10-14 | 2003-04-15 | 2003-10-15 | $7700.00 | Window Closed / Lapsed |