US4604731A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output circuit for a semiconductor memory device
Assignee: Shibaura Electronics Co Ltd
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Filing: 1983-09-02
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Granted: 1986-08-05
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Expires: 2003-09-02
Abstract
Abstract An output circuit for a semiconductor memory device including a preset circuit connected to a data output terminal and adapted to set a potential on the data output terminal to a potential between a potential of a first potential supply terminal and a potential of a second supply terminal during a preparative period for read preceding a data readout from a memory cell whereby the potential level on the data output terminal reaches a "H" level or a "L" level. Thus, the output circuit with high speed readout operation and with high reliability by means of being free from the instability caused by an output noise can be obtained.
Inventors
- 👤 Satoshi Konishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:21
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/106; G11C7/22
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
199 words
An output circuit for a semiconductor memory device, comprising: first and second potential supply terminals; a data signal input terminal for receiving a data signal read out of a memory cell; a control signal input terminal for receiving a control signal; a signal output terminal; a first transistor connected between the first potential supply terminal and the signal output terminal; a second transistor connected between the second potential supply terminal and the signal output terminal; a preset circuit including of a third transistor connected between the signal output terminal and the first potential supply terminal and a fourth transistor connected between the signal output terminal and the second potential supply terminal; a control circuit for controlling the first and second transistors according to the data signal input to the data signal input terminal and the control signal input to the control signal input terminal; and preset circuit control means for presetting the third and fourth transistors during a preparative period for read preceding the data readout from the memory cell, to set a potential on the signal output terminal to a potential between a potential of the first potential supply source and that of the second potential supply source.
Claim 2
Dependent Claim
199 words
An output circuit for a semiconductor memory device, comprising: first and second potential supply terminals; a data signal input terminal for receiving a data signal read out of a memory cell; a control signal input terminal for receiving a control signal; a signal output terminal; a first transistor connected between the first potential supply terminal and the signal output terminal; a second transistor connected between the second potential supply terminal and the signal output terminal; a preset circuit including of a third transistor connected between the signal output terminal and the first potential supply terminal and a fourth transistor connected between the signal output terminal and the second potential supply terminal; a control circuit for controlling the first and second transistors according to the data signal input to the data signal input terminal and the control signal input to the control signal input terminal; and preset circuit control means for presetting the third and fourth transistors during a preparative period for read preceding the data readout from the memory cell, to set a potential on the signal output terminal to a potential between a potential of the first potential supply source and that of the second potential supply source.
Claim 3
Dependent Claim
22 words
An output circuit of claim 1, wherein said preparative period for read preceding the data readout includes a bit line precharge period.
Claim 4
Dependent Claim
90 words
An output circuit of claim 1, wherein said control circuit comprises a latch circuit for latching said data signal, a NOR gate connected to receive an output of the latch circuit and said control signal, a NAND gate connected to receive an output of the latch circuit and an inverted replica of said control signal, a first inverter connected to invert the output of the NOR gate and control the first transistor, and a second inverter connected to invert the output of the NAND gate and control the second transistor.
Claim 5
Dependent Claim
32 words
An output circuit of claim 3, wherein said first transistor is a MOS transistor of a first conductivity type and said second transistor is a MOS transistor of a second conductivity type.
Claim 6
Dependent Claim
56 words
An output circuit of claim 3, wherein said control signal is produced through a NOR gate and an inverter for inverting an output of said NOR gate, said NOR gate having a first input terminal connected to receive a bit line precharging control signal and a second input terminal connected to receive a write command signal.
Claim 7
Dependent Claim
71 words
An output circuit of claim 1, wherein said preset circuit control means comprises an inverter for inverting the data signal, a NOR gate connected to receive an output of said inverter and a control signal and to control the third transistor by an output thereof, and a NAND gate connected to receive an output of said inverter and an inverted replica of said control signal and to control the fourth transistor.
Claim 8
Dependent Claim
26 words
An output circuit of claim 6, wherein said third transistor is of a second conductivity type and said fourth transistor is of a first conductivity type.
Claim 9
Dependent Claim
49 words
An output circuit of claim 6, wherein said control signal is generated by a NAND gate having a first input terminal connected to receive a signal based on a bit line control signal and a second input terminal connected to receive said inverted replica of said write command signal.
Claim 10
Dependent Claim
43 words
An output circuit of claim 1, wherein a ratio of maximum conductance value of said first transistor to that of said fourth transistor is substantially equal to a ratio of maximum conductance value of said second transistor to that of said third transistor.
Claim 11
Dependent Claim
43 words
An output circuit of claim 1, wherein the potential on said signal output terminal which is set by said preset circuit is an intermediate potential between the potential of said first potential supply terminal and the potential of said second potential supply terminal.
Claim 12
Dependent Claim
36 words
An output circuit of claim 1, wherein said control circuit and preset circuit control means are controlled by a control signal which is based on a signal generated by detecting a transistion of an address signal.
Claim 13
Dependent Claim
91 words
An output circuit of claim 1, wherein said control circuit comprises a latch circuit for latching said data signal, a NOR gate connected to receive an output of the latch circuit and a control signal, a NAND gate connected to receive the output of said latch circuit and an inverted replica of said control signal, first and second inverters connected to provide an output of said NOR gate to said first transistor therethrough, and a third inverter connected to invert an output of said NAND gate and control said second transistor.
Claim 14
Dependent Claim
26 words
An output circuit of claim 12, wherein said first transistor includes an intrinsic type MOS transistor and said second transistor includes an enhancement type MOS transistor.
Claim 15
Dependent Claim
59 words
An output circuit of claim 12, wherein said control signal is produced through a NOR gate and an inverter for inverting an output of said NOR gate, said NOR gate having a first input terminal connected to receive a signal based on a bit line control signal and a second input terminal connected to receive a write command signal.
Claim 16
Dependent Claim
68 words
An output circuit of claim 1, wherein said preset circuit control means comprises a NAND gate having a first input terminal connected to receive a signal based on a bit line control signal and a second input terminal connected to receive an inverted replica of a write command signal, and an inverter connected to invert an output of the NAND gate and control said third and fourth transistors.
Claim 17
Dependent Claim
17 words
An output circuit of claim 15, wherein said third and fourth transistors includes enhancement type MOS transistors.
Claim 18
Dependent Claim
31 words
An output circuit of claim 15, wherein said third and fourth transistors are formed such that their conduction resistances are substantially equal to each other when they are both turned ON.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-04 | 1990-02-03 | 1990-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-04 | 1994-02-03 | 1994-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-04 | 1998-02-03 | 1998-08-05 | $7700.00 | Window Closed / Lapsed |