US4096584A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low power/high speed static ram
Assignee: Intel Corp
•
Filing: 1977-01-31
•
Granted: 1978-06-20
•
Expires: 1997-01-31
Abstract
Abstract An integrated circuit, metal-oxide-semiconductor (MOS) static random-access memory (RAM) with a power-down mode is described. The bistable memory cells employed in the memory include low conductivity, depletion mode transistors used as loads. "Zero" threshold voltage devices are employed on a low body-effect substrate to permit the powering-down of many circuits in the memory without affecting circuit performance. Several circuits employing these zero threshold devices are described.
Inventors
- 👤 William H. Owen, III
- 👤 Kim R. Kokkonen
- 👤 Richard D. Pashley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:34
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
213 words
An integrated circuit, metal-oxide-semiconductor (MOS), random-access static memory comprising: a plurality of bistable memory cells; input and output means for communicating with said memory cells; power-down means for reducing the power consumed by said memory when said memory is in a standby mode, coupled to said input and output means; said memory including a plurality of enhancement mode MOS device, a first plurality of depletion mode MOS devices, a second plurality of depletion mode MOS devices, said second plurality of depletion mode MOS devices being less conductive than said first plurality, and a plurality of low threshold MOS devices, said low threshold MOS devices having a threshold voltage of approximately zero volts; said memory cells including in series one of said enhancement mode MOS devices and one of said second plurality of depletion mode MOS devices, said depletion mode device being employed as a load; said input and output means employing a plurality of said low threshold MOS devices coupled to receive a signal from said power-down means to reduce current flow in said input and output means during standby mode, said low threshold MOS devices coupled in series with said enhancement mode devices and said first depletion mode devices; whereby said memory is a fast random-access, static memory having low power consumption.
Claim 2
Dependent Claim
213 words
An integrated circuit, metal-oxide-semiconductor (MOS), random-access static memory comprising: a plurality of bistable memory cells; input and output means for communicating with said memory cells; power-down means for reducing the power consumed by said memory when said memory is in a standby mode, coupled to said input and output means; said memory including a plurality of enhancement mode MOS device, a first plurality of depletion mode MOS devices, a second plurality of depletion mode MOS devices, said second plurality of depletion mode MOS devices being less conductive than said first plurality, and a plurality of low threshold MOS devices, said low threshold MOS devices having a threshold voltage of approximately zero volts; said memory cells including in series one of said enhancement mode MOS devices and one of said second plurality of depletion mode MOS devices, said depletion mode device being employed as a load; said input and output means employing a plurality of said low threshold MOS devices coupled to receive a signal from said power-down means to reduce current flow in said input and output means during standby mode, said low threshold MOS devices coupled in series with said enhancement mode devices and said first depletion mode devices; whereby said memory is a fast random-access, static memory having low power consumption.
Claim 3
Dependent Claim
45 words
The memory defined by claim 1 wherein said power-down means includes a buffer which receives an external signal and which provides an enabling signal for said memory, said enabling signal coupled to said plurality of said low threshold devices of said input and output means.
Claim 4
Dependent Claim
28 words
The memory defined by claim 2 wherein said memory cells are arranged in two sections each of which include 64 row lines and 32 pairs of column lines.
Claim 5
Dependent Claim
45 words
The memory defined by claim 2 wherein said input and output means includes a latch means for receiving output data from said memory, said latch means providing a signal to said buffer to initiate said standby mode once data is received by said latch means.
Claim 6
Dependent Claim
27 words
The memory defined by claim 1 wherein said input and output means includes a plurality of Y-decoders which couple selected column lines with a bidirectional data bus.
Claim 7
Dependent Claim
25 words
The memory defined by claim 5 wherein each of said Y-decoders includes bootstrapping means for bootstrapping the gate of one of said low threshold devices.
Claim 8
Dependent Claim
24 words
The memory defined by claim 1 wherein said input and output means includes a data-out buffer which is selectively coupled to said memory cells.
Claim 9
Dependent Claim
15 words
The memory defined by claim 7 wherein said data-out buffer comprises a bistable, differential circuit.
Claim 10
Dependent Claim
27 words
The memory defined by claim 8 wherein said data-out buffer includes means for pre-setting said buffer in one of two stable states when said buffer is activated.
Claim 11
Dependent Claim
20 words
The memory defined by claim 9 wherein the output of said data-out buffer is high when said buffer is preset.
References Cited (Backward Citations)
US3703710A
Cited
US3848237A
Cited
US3906464A
Cited
US3995172A
Cited
US3969708A
Cited
US4019068A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-19 | 1981-12-19 | 1982-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-19 | 1985-12-19 | 1986-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-19 | 1989-12-19 | 1990-06-20 | $7700.00 | Window Closed / Lapsed |