Semiconductor memory

Claim 2

A semiconductor memory comprising: a plurality of memory sub-systems each including at least one semiconductor memory section; common power supply means for supplying drive power to a selected one of said memory sub-systems; switching means provided to said respective memory sub-systems and actuated with a select signal to select the corresponding one of said memory sub-systems, said switching means including a field effect transistor; means for connecting said common power supply means to the selected memory sub-system; and means for supplying the select signal to the respective switching means.

Claim 3

A semiconductor memory comprising: a plurality of memory sub-systems each including at least one semiconductor memory section; common power supply means for supplying drive power to a selected one of said memory sub-systems; switching means provided to said respective memory sub-systems and actuated with a select signal to select the corresponding one of said memory sub-systems, said switching means including a field effect transistor; means for connecting said common power supply means to the selected memory sub-system; and means for supplying the select signal to the respective switching means.

Claim 4

A semiconductor memory comprising: a plurality of memory sub-systems each including at least one semiconductor memory section; common power supply means for supplying drive power to a selected one of said memory sub-systems; switching means provided to said respective memory sub-systems and actuated with a select signal to select the corresponding one of said memory sub-systems, said switching means including a field effect transistor; means for connecting said common power supply means to the selected memory sub-system; and means for supplying the select signal to the respective switching means.

Claim 5

A semiconductor memory according to claim 1, wherein said connecting means comprises at least one field effect transistor.

Claim 6

A semiconductor memory according to claim 2, wherein said memory section includes a plurality of memory elements and said connecting means comprises a plurality of field effect transistors provided to the respective memory elements.

Claim 7

A semiconductor memory according to claim 3, wherein said switching means and connecting means comprise a first field effect transistor having an input terminal and first and second output terminals, a plurality of second field effect transistors provided to the respective memory elements, each of said second field effect transistors having an input terminal and first and second output terminals, a switch source, a resistor connected between said switch source and the second output terminal of said first field effect transistor, means for connecting said select signal supply means to said input terminal of said first field effect transistor, means for connecting the first output terminal of said first field effect transistor to ground, means for connecting the second output terminal of said second field effect transistors to said common power supply means, means for connecting the second output terminal of said first field effect transistor to the input terminals of said second field effect transistors and means for connecting the first output terminals of said second field effect transistors to the respective memory elements.

Claim 8

A semiconductor memory comprising: a plurality of memory sub-systems each including at least one semiconductor memory section; a first power supply means for supplying drive power to a selected one of said memory sub-systems; a second power supply means for supplying power sufficient to maintain the memorized state of said semiconductor memory section of non-selected memory sub-systems; switching means including a field effect transistor and being provided to the respective memory subsystems, said switching means being actuated with a select signal to select the corresponding one of said sub-systems; means for connecting the selected sub-system to said first power supply means; means for connecting the non-selected sub-systems to said second power supply means; and means for supplying the select signal to said switching means.

Claim 9

A semiconductor memory comprising: a plurality of memory sub-systems each including at least one semiconductor memory section; a first power supply means for supplying drive power to a selected one of said memory sub-systems; a second power supply means for supplying power sufficient to maintain the memorized state of said semiconductor memory section of non-selected memory sub-systems; switching means including a field effect transistor and being provided to the respective memory subsystems, said switching means being actuated with a select signal to select the corresponding one of said sub-systems; means for connecting the selected sub-system to said first power supply means; means for connecting the non-selected sub-systems to said second power supply means; and means for supplying the select signal to said switching means.

Claim 10

A semiconductor memory according to claim 5, wherein said connecting means include a field effect transistor, respectively.

Claim 11

A semiconductor memory according to claim 6, wherein said switching means and connecting means comprise first, second and third field effect transistors each having an input terminal and first and second output terminals, a resistor connected between the second output terminal of said first field effect transistor and the second output terminal of said second field effect transistor, means for connecting the second output terminals of saiD second and third field effect transistors to said first and second power supply means, respectively, means for connecting the select signal supply means to input terminals of said first and third field effect transistors, means for connecting the second output terminal of said first field effect transistor to the input terminal of said second field effect transistor, means for connecting the first output terminal of said first field effect transistor to ground, and means for connecting the first output terminals of said second and third field effect transistor to the corresponding one of said memory sub-systems.

Claim 12

A semiconductor memory comprising: a plurality of memory sub-systems, each of which includes at least one semiconductor section; first means, coupled to each of said sub-systems, for supplying driving power to a selected one of said sub-systems; second means, connected between said first means and said sub-systems, for selectively switching driving power from said first means to one of said memory sub-systems, comprising a transistor switching circuit including first and second transistors connected in series, the first one of which being responsive to a sub-system selection signal for energizing the second transistor, which is connected to said first means, and for controlling the supply of driving power from said first means by way of said second transistor to a selected memory sub-system.

Claim 13

A semiconductor memory comprising: a plurality of memory sub-systems, each of which includes at least one semiconductor section; first means, coupled to each of said sub-systems, for supplying driving power to a selected one of said sub-systems; second means, connected between said first means and said sub-systems, for selectively switching driving power from said first means to one of said memory sub-systems, comprising a transistor switching circuit including first and second transistors connected in series, the first one of which being responsive to a sub-system selection signal for energizing the second transistor, which is connected to said first means, and for controlling the supply of driving power from said first means by way of said second transistor to a selected memory sub-system.

Claim 14

A semiconductor memory according to claim 8, wherein said first and second transistors comprise field effect transistors, the series connection therebetween being effected from one of the source and drain electrodes of said first transistor to the gate electrode of said second transistor, said first means being connected to one of the source and drain electrodes of said second field effect transistor, while the other of said source and drain electrodes thereof is connected to a memory sub-system.

Claim 15

A semiconductor memory according to claim 9, wherein said second means further includes a control terminal connected to the gate electrode of said first field effect transistor, to which said sub-system selection signal is applied.