US3573758A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-linear impedance means for transistors connected to each other and to a common power source
Assignee: International Business Machines Corp
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Filing: 1969-02-27
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Granted: 1971-04-06
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Expires: 1989-02-27
Abstract
Abstract Each of the pair of transistors of a flip-flop storage cell has its collector connected through a nonlinear impedance means to a low constant current source when the cell is in an inactive condition. The nonlinear impedance means for the conducting transistor maintains the ratio of the load impedance means to the base-emitter impedance of the conducting transistor greater than one to maintain the transistors of the cell in the desired bistable state when the transistors are connected to the low constant current source through the nonlinear impedance means.
Inventors
- 👤 Robert A Henle
- 👤 W David Pricer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:36
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/4116
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
180 words
In combination: at least two transistors connected to each other in such a manner that the conducting and nonconducting state of each transistor is related to the conducting and nonconducting state of the other transistor with at least one of the transistors being in a conducting state; a low power level source; a high power level source; load impedance means for each of said transistors; means to connect each of said transistors through said load impedance means to one of said low power level source and said high power level source; each of said load impedance means including nonlinear impedance means, said nonlinear impedance means being effective at least when said transistors are connected to said low power level source; and said nonlinear impedance means having its impedance variable with the current flow therethrough to maintain the ratio of said load impedance means of each of said transistors that is conducting to its base-emitter impedance greater than one to maintain each of said conducting transistors in its conducting state when said transistors are connected to said low power level source.
Claim 2
Dependent Claim
180 words
In combination: at least two transistors connected to each other in such a manner that the conducting and nonconducting state of each transistor is related to the conducting and nonconducting state of the other transistor with at least one of the transistors being in a conducting state; a low power level source; a high power level source; load impedance means for each of said transistors; means to connect each of said transistors through said load impedance means to one of said low power level source and said high power level source; each of said load impedance means including nonlinear impedance means, said nonlinear impedance means being effective at least when said transistors are connected to said low power level source; and said nonlinear impedance means having its impedance variable with the current flow therethrough to maintain the ratio of said load impedance means of each of said transistors that is conducting to its base-emitter impedance greater than one to maintain each of said conducting transistors in its conducting state when said transistors are connected to said low power level source.
Claim 3
Dependent Claim
28 words
The combination according to claim 1 in which said load impedance means includes said nonlinear impedance means when said transistors are connected to said high power level source.
Claim 4
Dependent Claim
45 words
The combination according to claim 1 in which: each of said impedance means includes a resistor; means to connect said resistor directly to said high power level source; and means to connect said resistor to said low power level source through said nonlinear impedance means.
Claim 5
Dependent Claim
18 words
The combination according to claim 1 in which said transistors comprise two transistors connected in a flip-flop arrangement.
Claim 6
Dependent Claim
17 words
The combination according to claim 1 in which said nonlinear impedance means includes at least one diode.
Claim 7
Dependent Claim
18 words
The combination according to claim 1 in which said nonlinear impedance means includes two diodes connected in series.
Claim 8
Dependent Claim
18 words
The combination according to claim 1 in which said transistors are formed in a monolithic integrated semiconductor array.
Claim 9
Dependent Claim
181 words
A memory device including: a plurality of storage cells; a first plurality of power sources; a second plurality of power sources; each of said cells being connected to one of said first plurality of power sources and one of said second plurality of power sources so that no cell is connected to the same of said first plurality of power sources and said second plurality of power sources whereby only one of said cells may be activated due to one of said first plurality of power sources and one of said second plurality of power sources being simultaneously activated; and each of said cells including nonlinear impedance means between its connection to one of said first plurality of power sources and its connection to one of said second plurality of power sources, said nonlinear impedance means reducing the power consumption of all other cells in the memory device to less than half the power consumption of said cell that has said one of said first plurality of power sources and said one of said second plurality of power sources connected thereto.
Claim 10
Dependent Claim
181 words
A memory device including: a plurality of storage cells; a first plurality of power sources; a second plurality of power sources; each of said cells being connected to one of said first plurality of power sources and one of said second plurality of power sources so that no cell is connected to the same of said first plurality of power sources and said second plurality of power sources whereby only one of said cells may be activated due to one of said first plurality of power sources and one of said second plurality of power sources being simultaneously activated; and each of said cells including nonlinear impedance means between its connection to one of said first plurality of power sources and its connection to one of said second plurality of power sources, said nonlinear impedance means reducing the power consumption of all other cells in the memory device to less than half the power consumption of said cell that has said one of said first plurality of power sources and said one of said second plurality of power sources connected thereto.
Claim 11
Dependent Claim
19 words
The memory device according to claim 8 in which said cells are formed in a monolithic integrated semiconductor array.
Claim 12
Dependent Claim
58 words
The memory device according to claim 8 in which: said cells are arranged in columns and rows; each of said columns of said cells being connected to a different one of said first plurality of power sources; and each of said rows of said cells being connected to a different one of said second plurality of power sources.
Claim 13
Dependent Claim
18 words
The memory device according to claim 8 in which said nonlinear impedance means includes at least one diode.
Claim 14
Dependent Claim
19 words
The memory device according to claim 8 in which said nonlinear impedance means includes two diodes connected in series.
Claim 15
Dependent Claim
44 words
The memory device according to claim 8 in which: each of said cells comprises two transistors connected in a flip-flop arrangement; and each of said transistors being connected to one of said first and second plurality of power sources through said nonlinear impedance means.
Claim 16
Dependent Claim
18 words
The combination according to claim 2 in which said transistors comprise two transistors connected in a flip-flop arrangement.
Claim 17
Dependent Claim
17 words
The combination according to claim 14 in which said nonlinear impedance means includes at least one diode.
Claim 18
Dependent Claim
18 words
The combination according to claim 15 in which said transistors are formed in a monolithic integrated semiconductor array.
Claim 19
Dependent Claim
18 words
The combination according to claim 14 in which said nonlinear impedance means includes two diodes connected in series.
Claim 20
Dependent Claim
18 words
The combination according to claim 17 in which said transistors are formed in a monolithic integrated semiconductor array.
Claim 21
Dependent Claim
17 words
The combination according to claim 2 in which said nonlinear impedance means includes at least one diode.
Claim 22
Dependent Claim
18 words
The combination according to claim 2 in which said nonlinear impedance means includes two diodes connected in series.
Claim 23
Dependent Claim
17 words
The combination according to claim 4 in which said nonlinear impedance means includes at least one diode.
Claim 24
Dependent Claim
18 words
The combination according to claim 21 in which said transistors are formed in a monolithic integrated semiconductor array.
Claim 25
Dependent Claim
18 words
The combination according to claim 4 in which said nonlinear impedance means includes two diodes connected in series.
Claim 26
Dependent Claim
18 words
The combination according to claim 23 in which said transistors are formed in a monolithic integrated semiconductor array.
Claim 27
Dependent Claim
58 words
The memory device according to claim 9 in which: said cells are arranged in columns and rows; each of said columns of said cells being connected to a different one of said first plurality of power sources; and each of said rows of said cells being connected to a different one of said second plurality of power sources.
Claim 28
Dependent Claim
18 words
The memory device according to claim 25 in which said nonlinear impedance means includes at least one diode.
Claim 29
Dependent Claim
19 words
The memory device according to claim 25 in which said nonlinear impedance means includes two diodes connected in series.
Claim 30
Dependent Claim
44 words
The memory device according to claim 25 in which: each of said cells comprises two transistors connected in a flip-flop arrangement; and each of said transistors being connected to one of said first and second plurality of power sources through said nonlinear impedance means.
Claim 31
Dependent Claim
18 words
The memory device according to claim 9 in which said nonlinear impedance means includes at least one diode.
Claim 32
Dependent Claim
19 words
The memory device according to claim 9 in which said nonlinear impedance means includes two diodes connected in series.
Claim 33
Dependent Claim
44 words
The memory device according to claim 9 in which: each of said cells comprises two transistors connected in a flip-flop arrangement; and each of said transistors being connected to one of said first and second plurality of power sources through said nonlinear impedance means.
Claim 34
Dependent Claim
18 words
The memory device according to claim 10 in which said nonlinear impedance means includes at least one diode.
Claim 35
Dependent Claim
19 words
The memory device according to claim 10 in which said nonlinear impedancE means includes two diodes connected in series.
Claim 36
Dependent Claim
44 words
The memory device according to claim 10 in which: each of said cells comprises two transistors connected in a flip-flop arrangement; and each of said transistors being connected to one of said first and second plurality of power sources through said nonlinear impedance means.
Claim 37
Dependent Claim
44 words
The memory device according to claim 11 in which: each of said cells comprises two transistors connected in a flip-flop arrangement; and each of said transistors being connected to one of said first and second plurality of power sources through said nonlinear impedance means.
Claim 38
Dependent Claim
44 words
The memory device according to claim 12 in which: each of said cells comprises two transistors connected in a flip-flop arrangement; and each of said transistors being connected to one of said first and second plurality of power sources through said nonlinear impedance means.
References Cited (Backward Citations)
US3363115A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |