Burst address sequence generator

Claim 1

A pulse train burst sequence generator for generating 2 n pulse train address sequences from a starting address, A(0, . . . , m+n-1), where n is an integer greater than 1, comprising: delay means having an input coupled to a column address strobe (CAS#) signal, said delay means producing at its output a delayed copy of the CAS# signal, said delay being greater than the retaining time of a column address; a phase inverter coupled to the delayed CAS# signal, for producing an inverted delayed CAS# signal; an n-bit binary up counter for generating an ascending sequence of numbers, having a first input terminal coupled to a signal for initializing the count to zero, a second input terminal coupled to the inverted delayed CAS# signal for triggering a count operation of the counter, and an output terminal comprising n count signals, C(0, . . . , n-1); a logic device coupled to the n count signals (C(0, . . . , n-1)), n address signals (A(m, . . . , m+n-1)), n row address signals (RA(0, 1, . . . , n-1)), a multiplexer selection signal (MUX), and an address latch enable signal (ALE), for producing n dynamic memory address signals (MA(0, . . . , n-1)), wherein the logic device includes n latches coupled to the n address signal (A(m, . . . , m+n-1)) for storing an initial value of the n address signals (LA(m, . . . , m+n-1)), and wherein further each dynamic memory address signal MA(i) (where i is an integer from 0 to n-1) has the following relationship to the inputs: MA(i)=Mux*RA(i)+/Mux*A(m+1)*/ALE+/Mux*(LA(m+i):+:C(i))*ALE, where "*" represents a logical AND operation, "+" represents a logical OR operation, "/" represents a logical NOT operation, and ":+:" represents a logical EXCLUSIVE OR operation.