Semiconductor memory device and operating method thereof with transfer transistor used as a holding means

Claim 2

A semiconductor memory device comprising: memory cell array comprising a plurality of memory cells arranged in rows and columns; internal address generating means responsive to an externally applied address signal for generating an internal column address signal; first selecting means responsive to said internal column address signal generated by said internal address generating means for generating a selecting signal which simultaneously selects a plurality of columns in said memory cell array; holding means for holding said selecting signal generated by said first selecting means; second selecting means for sequentially selecting said plurality of column simultaneously selected by said selecting signal held by said holding means; writing means for applying external information to the column selected by said second selecting means; and timing control means for performing timing control in such a manner that during the selecting operation by said second selecting means, the selecting operation by said first selecting means is performed in response to the subsequent internal column address signal.

Claim 3

The semiconductor memory device according to claim 1, wherein said internal address generating means is responsive to an externally applied column address signal for initially generating an internal column address signal equal to said column address signal, and thereafter sequentially generating internal column address signals following said internal column address signal.

Claim 4

The semiconductor memory device according to claim 1, wherein said internal address generating means comprises: binary counter means for receiving a part of said externally applied address signal and sequentially counting up the same; and address buffer means for initially outputting said part of said externally applied address signal as an internal column address signal, and thereafter sequentially outputting outputs of said binary counting means as internal column address signals.

Claim 5

The semiconductor memory device according to claim 3, wherein said second selecting means comprises: a decoder decoding the remaining part of said externally applied column address signal and outputting the decoded signal; a shift register holding said decoded signal from said decoder and sequentially shifting the same; and a selector responsive to said decoded signal held by said shift register for connecting said writing means to any one of said plurality of columns simultaneously selected by said selecting signal.

Claim 6

The semiconductor memory device according to claim 4, wherein said first selecting means comprises a column decoder decoding said internal column address signal.

Claim 7

The semiconductor memory device according to claim 5, wherein said holding means comprise a plurality of latch circuits connected between outputs of said address buffer means and said plurality of columns.

Claim 8

The semiconductor memory device according to claim 6, wherein said writing means comprises an input terminal receiving externally applied information and an input buffer.

Claim 9

The semiconductor memory device according to claim 1, which further comprises: third selecting means responsive to an externally applied address signal for selecting one row in said memory cell array.

Claim 10

The semiconductor memory device according to claim 1, which further comprises: second holding means for holding a plurality of pieces of information read out of a plurality of columns selected by said first selecting means; and third selecting means for sequentially selecting said plurality of pieces of information held by said second holding means; and wherein said timing control means performs timing control in such a manner that during information selecting operation by said third selecting means, selecting operation is performed by said first selecting means in response to the subsequent internal column address signal.

Claim 11

A semiconductor memory device comprising: memory cell array comprising a plurality of memory cells arranged in rows and columns; internal address generating means responsive to an externally applied address signal for generating an internal column address signal; first selecting means responsive to said internal column address signal generated from said internal address generating means for simultaneously selecting a plurality of columns in said memory cell array; holding means for holding a plurality of pieces of information read out of the plurality of columns selected by said first selecting means; second selecting means for sequentially selecting said plurality of pieces of information held by said holding means; and timing control means for performing timing control in such a manner that during information selecting operation by said second selecting means, selecting operation is performed by said first selecting means in response to the subsequent internal column address signal.

Claim 12

A semiconductor memory device comprising: memory cell array comprising a plurality of memory cells arranged in rows and columns; internal address generating means responsive to an externally applied address signal for generating an internal column address signal; first selecting means responsive to said internal column address signal generated from said internal address generating means for simultaneously selecting a plurality of columns in said memory cell array; holding means for holding a plurality of pieces of information read out of the plurality of columns selected by said first selecting means; second selecting means for sequentially selecting said plurality of pieces of information held by said holding means; and timing control means for performing timing control in such a manner that during information selecting operation by said second selecting means, selecting operation is performed by said first selecting means in response to the subsequent internal column address signal.

Claim 13

The semiconductor memory device according to claim 10, wherein said internal address generating means is responsive to an externally applied column address signal for initially generating an internal column address signal equal to said column address signal, and thereafter, sequentially generating internal column address signals following said internal column address signal.

Claim 14

The semiconductor memory device according to claim 10, wherein said internal address generating means comprises: binary counter means for receiving a part of said externally applied address signal and sequentially counting up the same; and address buffer means for initially outputting said part of said externally applied address signal as an internal column address signal, and thereafter, sequentially outputting outputs of said binary counting means as internal column address signals.

Claim 15

The semiconductor memory device according to claim 12, wherein said second selecting means comprises: a decoder decoding the remaining part of said externally applied address signal and outputting the decoded signal; a shift register holding said decoded signal from said decoder and sequentially shifting the same; and a selector responsive to said decoded signal held by said shift register for outputting any one of said plurality of pieces of information held by said holding means.

Claim 16

The semiconductor memory device according to claim 10, which further comprises: third selecting means responsive to an externally applied address signal for selecting one row in said memory cell array.

Claim 17

A semiconductor memory device comprising: memory cell array comprising a plurality of memory cells arranged in rows and columns; a plurality of information holding means each provided to correspond to each of said plurality of columns in said memory cell array for holding information; information transfer means for transferring information between said plurality of information holding means and said memory cell array; internal address generating means responsive to an externally applied column address signal for generating an internal column address signal; first selecting means responsive to said internal column address signal generated from said internal address generating means for generating a selecting signal which simultaneously selects any plurality of said plurality of information holding means; first holding means for holding said selecting signal generated by said first selecting means; second selecting means for sequentially selecting said plurality of columns simultaneously selected by said selecting signal held by said first holding means; writing means for applying information from the external to a column selected by said second selecting means; and timing control means for performing timing control in such a manner that during selecting operation by said second selecting means, selecting operation is performed by said first selecting means in response to the subsequent internal column address signal.

Claim 18

A semiconductor memory device comprising: memory cell array comprising a plurality of memory cells arranged in rows and columns; a plurality of information holding means each provided to correspond to each of said plurality of columns in said memory cell array for holding information; information transfer means for transferring information between said plurality of information holding means and said memory cell array; internal address generating means responsive to an externally applied column address signal for generating an internal column address signal; first selecting means responsive to said internal column address signal generated from said internal address generating means for generating a selecting signal which simultaneously selects any plurality of said plurality of information holding means; first holding means for holding said selecting signal generated by said first selecting means; second selecting means for sequentially selecting said plurality of columns simultaneously selected by said selecting signal held by said first holding means; writing means for applying information from the external to a column selected by said second selecting means; and timing control means for performing timing control in such a manner that during selecting operation by said second selecting means, selecting operation is performed by said first selecting means in response to the subsequent internal column address signal.

Claim 19

The semiconductor memory device according to claim 15, which further comprises: second holding means for holding a plurality of pieces of information read out of a plurality of information holding means selected by said first selecting means; and third selecting means for sequentially selecting said plurality of pieces of information held by said second holding means; and wherein said timing control means performs timing control in such a manner that during information selecting operation by said third selecting means, selecting operation is performed by said first selecting means in response to the subsequent internal column address signal.

Claim 20

An operating method of a semiconductor memory device which comprises a memory cell array comprising a plurality of memory cells arranged in rows and columns, comprising the steps of: generating an internal column address signal in response to an externally applied address signal; generating a selecting signal for simultaneously selecting a plurality of columns in said memory cell array in response to said internal column address signal; holding said selecting signal; sequentially selecting said plurality of columns simultaneously selected by said held selecting signal; applying information from the external to said selected column; and performing timing control in such a manner that during said sequential selecting operation, selecting operation is performed with respect to a plurality of columns in response to the subsequent internal column address signal.

Claim 21

An operating method of a semiconductor memory device which comprises a memory cell array comprising a plurality of memory cells arranged in rows and columns, comprising the steps of: generating an internal column address signal in response to an externally applied address signal; generating a selecting signal for simultaneously selecting a plurality of columns in said memory cell array in response to said internal column address signal; holding said selecting signal; sequentially selecting said plurality of columns simultaneously selected by said held selecting signal; applying information from the external to said selected column; and performing timing control in such a manner that during said sequential selecting operation, selecting operation is performed with respect to a plurality of columns in response to the subsequent internal column address signal.

Claim 22

An operating method of a semiconductor memory device which comprises a memory cell array comprising a plurality of memory cells arranged in rows and columns, comprising the steps of: generating an internal column address signal in response to an externally applied address signal, simultaneously selecting a plurality of columns in said memory cell array in response to said internal column address signal, holding a plurality of pieces of information read out of said selected plurality of columns; sequentially selecting said held plurality of pieces of information; and performing timing control in such a manner that during said sequential information selecting operation, selecting operation is performed with respect to a plurality of columns in response to the subsequent internal column address signal.

Claim 23

An operating method of a semiconductor memory device which comprises a memory cell array comprising a plurality of memory cells arranged in rows and columns, comprising the steps of: generating an internal column address signal in response to an externally applied address signal, simultaneously selecting a plurality of columns in said memory cell array in response to said internal column address signal, holding a plurality of pieces of information read out of said selected plurality of columns; sequentially selecting said held plurality of pieces of information; and performing timing control in such a manner that during said sequential information selecting operation, selecting operation is performed with respect to a plurality of columns in response to the subsequent internal column address signal.