Method for data transfer for a semiconductor memory using combined control signals to provide high speed transfer, and semiconductor memory for carrying out the method

Claim 2

In a method for data transfer between a plurality of memory cells and at least one input/output terminal of a semiconductor memory, in which a first memory cell address is defined for a data transfer by an address control signal, the improvement which comprises: controlling a data transfer operation with the address control signal and an output enable control signal by placing the address control signal in its active state and defining a first memory cell address, placing the output enable control signal in its active state, initiating the data transfer with regard to the first memory cell address after the address control signal and the output enable control signal have been placed in their active states, subsequently at least once placing the output enable control signal in its inactive state and back in its active state while maintaining the address control signal in its active state, and defining a further memory cell address each time the output enable control signal is placed back in its active state and proceeding with the data transfer with regard to the further memory cell address, and also defining a further memory cell address each time the output enable control signal is placed into its inactive state and proceeding with the data transfer with regard to the further memory cell address.

Claim 3

The method according to claim 1, which comprises terminating the data transfer by placing the address control signal into a state being opposite its active state.

Claim 4

In a method for data transfer between a plurality of memory cells and at least one input/output terminal of a semiconductor memory, in which a first memory cell address is defined for a data transfer by an address control signal, the improvement which comprises: controlling a data transfer operation with the address control signal and an output enable control signal by placing the address control signal in its active state and defining the first memory cell address, placing the output enable control signal in its active state, initiating the data transfer with regard to the first memory cell address after the address and output enable control signals have been placed in their active states, subsequently placing the address control signal into a state being opposite its active state while maintaining the output enable control signal in its active state, and defining a further memory cell address, and proceeding with the data transfer with regard to the further memory cell address.

Claim 5

In a method for data transfer between a plurality of memory cells and at least one input/output terminal of a semiconductor memory, in which a first memory cell address is defined for a data transfer by an address control signal, the improvement which comprises: controlling a data transfer operation with the address control signal and an output enable control signal by placing the address control signal in its active state and defining the first memory cell address, placing the output enable control signal in its active state, initiating the data transfer with regard to the first memory cell address after the address and output enable control signals have been placed in their active states, subsequently placing the address control signal into a state being opposite its active state while maintaining the output enable control signal in its active state, and defining a further memory cell address, and proceeding with the data transfer with regard to the further memory cell address.

Claim 6

The method according to claim 3, which comprises, subsequently to placing the address control signal into the state opposite its active state, at least once placing the address control signal into its active state while maintaining the output enable control signal in its active state; defining a further memory cell address each time the address control signal changes between its active state and the state opposite the active state; and proceeding with the data transfer with regard to each of the further memory cell addresses.

Claim 7

The method according to claim 3, which comprises terminating the data transfer by placing the output enable control signal into a state being opposite its active state.

Claim 8

In a semiconductor memory having a plurality of memory cells, at least one input/output terminal, including means for addressing the memory cells, means for defining memory cell addresses, and means for controlling a data transfer between the at least one input/output terminal and the memory cells, the improvement comprising: means for jointly controlling a data transfer operation with an address control signal and an output enable control signal, said controlling means including: means which define a first memory cell address by placing the address control signal into an active state, means which selectively place the output enable control signal in its active state, said defining means and said selectively placing means together being means for initiating the data transfer operation with regard to said first memory cell address by placing the control signals in their active states, means for at least once placing the output enable control signal into an inactive state and back into an active state while maintaining the address control signal in an active state, after the data transfer operation has been initiated, and said defining means defining a further memory cell address each time the output enable control signal assumes its active state and proceeding with the data transfer operation with regard to the further memory cell address, and said defining means defining a further memory cell address when the output enable control signal is placed in its inactive state while the address control signal is maintained in its active state, and wherein the data transfer operation is continued with regard to the further memory cell addresses.

Claim 9

In a semiconductor memory having a plurality of memory cells, at least one input/output terminal, including means for addressing the memory cells, means for defining memory cell addresses, and means for controlling a data transfer between the at least one input/output terminal and the memory cells, the improvement comprising: means for jointly controlling a data transfer operation with an address control signal and an output enable control signal, said controlling means including: means which define a first memory cell address by placing the address control signal into an active state, means which selectively place the output enable control signal in its active state, said defining means and said selectively placing means together being means for initiating the data transfer operation with regard to said first memory cell address by placing the control signals in their active states, means for at least once placing the output enable control signal into an inactive state and back into an active state while maintaining the address control signal in an active state, after the data transfer operation has been initiated, and said defining means defining a further memory cell address each time the output enable control signal assumes its active state and proceeding with the data transfer operation with regard to the further memory cell address, and said defining means defining a further memory cell address when the output enable control signal is placed in its inactive state while the address control signal is maintained in its active state, and wherein the data transfer operation is continued with regard to the further memory cell addresses.

Claim 10

The semiconductor memory according to claim 6, including means for terminating the data transfer operation by placing the address control signal into a state which is opposite the active state.

Claim 11

In a semiconductor memory having a plurality of memory cells, at least one input/output terminal, including means for addressing the memory cells, means for defining memory cells addresses, and means for controlling a data transfer between the at least one input/output terminal and the memory cells, the improvement comprising: means for jointly controlling a data transfer operation with an address control signal and an output enable control signal, said controlling means including: means which define a first memory cell address by placing the address control signal into an active state, means which selectively place the output enable control signal in its active state, said defining means and said selectively placing means together being means for initiating the data transfer operation with regard to said first memory cell address by placing the control signals into the active states, said defining means defining a further memory cell address after initiation of the data transfer operation by placing the address control signal into a state which is opposite its active state while maintaining the output enable signal in its active state, and continuing the data transfer operation with regard to the further memory cell address.

Claim 12

In a semiconductor memory having a plurality of memory cells, at least one input/output terminal, including means for addressing the memory cells, means for defining memory cells addresses, and means for controlling a data transfer between the at least one input/output terminal and the memory cells, the improvement comprising: means for jointly controlling a data transfer operation with an address control signal and an output enable control signal, said controlling means including: means which define a first memory cell address by placing the address control signal into an active state, means which selectively place the output enable control signal in its active state, said defining means and said selectively placing means together being means for initiating the data transfer operation with regard to said first memory cell address by placing the control signals into the active states, said defining means defining a further memory cell address after initiation of the data transfer operation by placing the address control signal into a state which is opposite its active state while maintaining the output enable signal in its active state, and continuing the data transfer operation with regard to the further memory cell address.

Claim 13

The semiconductor memory according to claim 8, wherein said defining means place the address control signal at least once into its active state and the state opposite the active state for further continuing the data transfer operation while the output enable signal is maintained in its active state; wherein said defining means defines a further memory cell address each time the address control signal is placed into its active state and each time the address control signal is placed into the state opposite thereto; and wherein the data transfer operation is continued for each of the further defined memory cell addresses.

Claim 14

The semiconductor memory according to claim 8, including means for terminating the data transfer operation by placing the output enable control signal into a state opposite its active state.