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US5807769A
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Methods of making thin film transistors
Assignee: Micron Technology Inc
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Filing: 1995-06-06
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Granted: 1998-09-15
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Expires: 2015-06-06
Abstract
Abstract A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.
Inventors
- 👤 Charles H. Dennison
- 👤 Monte Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10B; H10B10/00; H10B10/12; H10B10/125; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
129 words
A method of forming a top gated thin film field effect transistor comprising: forming a thin film transistor layer over a substrate, the layer comprising first and second source/drain areas separated by an intervening channel region; forming a conductive layer of material over the thin film transistor layer; removing conductive layer portions sufficient to define at least one source/drain block over one of the source/drain areas, the source/drain block having a sidewall; and forming a top gate over the substrate, the top gate having a conductive sidewall, the source/drain block sidewall and the top gate conductive sidewall defining a region of overlap between the source/drain block and the top gate, wherein material of the source/drain block is disposed over material of the top gate within the region of overlap.
Claim 2
Independent Claim
129 words
A method of forming a top gated thin film field effect transistor comprising: forming a thin film transistor layer over a substrate, the layer comprising first and second source/drain areas separated by an intervening channel region; forming a conductive layer of material over the thin film transistor layer; removing conductive layer portions sufficient to define at least one source/drain block over one of the source/drain areas, the source/drain block having a sidewall; and forming a top gate over the substrate, the top gate having a conductive sidewall, the source/drain block sidewall and the top gate conductive sidewall defining a region of overlap between the source/drain block and the top gate, wherein material of the source/drain block is disposed over material of the top gate within the region of overlap.
Claim 3
Dependent Claim
98 words
The method of claim 1, wherein: the removing of the conductive layer portions defines another source/drain block over the other of the source/drain areas, the another source/drain block having a sidewall; and the forming of the top gate comprises forming another top gate sidewall, the another source/drain block sidewall and the another top gate sidewall defining a region of overlap between the another source/drain block and the top gate, wherein material of the another source/drain block is disposed over material of the top gate within the region of overlap between the another source/drain block and the top gate.
Claim 4
Independent Claim
115 words
A method of forming a top gated thin film field effect transistor comprising: forming a thin film transistor layer over a substrate, the layer comprising first and second source/drain areas separated by an intervening channel region; forming a top gate over the substrate, the top gate having a conductive sidewall; after forming the top gate, forming a conductive layer of material over the thin film transistor layer; and removing conductive layer portions sufficient to define at least one source/drain block over one of the source/drain areas, the source/drain block having a sidewall, the source/drain block sidewall and the top gate conductive sidewall defining a region of overlap between the source/drain block and the top gate.
Claim 5
Independent Claim
115 words
A method of forming a top gated thin film field effect transistor comprising: forming a thin film transistor layer over a substrate, the layer comprising first and second source/drain areas separated by an intervening channel region; forming a top gate over the substrate, the top gate having a conductive sidewall; after forming the top gate, forming a conductive layer of material over the thin film transistor layer; and removing conductive layer portions sufficient to define at least one source/drain block over one of the source/drain areas, the source/drain block having a sidewall, the source/drain block sidewall and the top gate conductive sidewall defining a region of overlap between the source/drain block and the top gate.
Claim 6
Dependent Claim
26 words
The method of claim 1, wherein the forming of the conductive layer of material comprises forming a layer of polysilicon over the thin film transistor layer.
Claim 7
Dependent Claim
27 words
The method of claim 1, wherein the forming of the conductive layer of material comprises forming a layer of conductively-doped polysilicon over the thin film transistor layer.
Claim 8
Dependent Claim
26 words
The method of claim 2, wherein the forming of the conductive layer of material comprises forming a layer of polysilicon over the thin film transistor layer.
Claim 9
Dependent Claim
27 words
The method of claim 2, wherein the forming of the conductive layer of material comprises forming a layer of conductively-doped polysilicon over the thin film transistor layer.
Claim 10
Dependent Claim
26 words
The method of claim 3, wherein the forming of the conductive layer of material comprises forming a layer of polysilicon over the thin film transistor layer.
Claim 11
Dependent Claim
27 words
The method of claim 3, wherein the forming of the conductive layer of material comprises forming a layer of conductively-doped polysilicon over the thin film transistor layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |