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US5498557A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making SRAM to improve interface state density utilizing PMOS TFT

Assignee: Sony Corp
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Filing: 1994-04-14
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Granted: 1996-03-12
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Expires: 2014-04-14
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Abstract

Abstract A thin film transistor in which a device active layer is formed on an insulation film. In which an interface state density present at the interface between the active layer and the insulation film is set to less than 1×10 11 /cm 2 . The characteristics of TFT can be enhanced by decreasing the leak current and SRAM memory cell can be provided with easy design for the process and the structure while avoiding increase in the resistance and additional capacitance and ensuring voltage withstand.

Inventors

  • 👤 Michio Negishi
  • 👤 Ihachi Naiki
  • 👤 Masayoshi Sasaki
  • 👤 Tadayuki Kimura

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 04:20
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10B; H10B69/00; H10B10/00; H10B10/12; H10B10/125; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/6737; H10D30/6739; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D64/01302; H10D64/01332; H10D86/00; H10D86/01; H10D86/201; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S438/00; Y10S438/91

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 284 words
A method of forming a SRAM memory cell comprising the steps of: forming a polysilicon film on a silicon oxide substrate by chemical vapor deposition; removing portions of the polysilicon film to form holes; implanting boron difluoride ions into the remaining portions of the polysilicon film to form a gate electrode and source and drain electrodes; forming a first silicon oxide insulation film on the gate electrode and source and drain electrodes by chemical vapor deposition; removing portions of the first silicon oxide film on the source and drain electrodes by photolithography and etching to form contact holes; forming an amorphous silicon film on the inside of the contact holes and the surface of the first silicon oxide insulation film; performing annealing treatment on said amorphous silicon film to convert said amorphous silicon film into a polysilicon film; removing portions of the polysilicon film with the remaining portions serving as an active region; oxidizing the active region at 850° C. to form a second silicon oxide film on the active region and simultaneously form a gate oxide film at the interface between the active region and the first silicon oxide film; forming source and drain regions adjacent opposing sides of the gate electrode by ion implantation of a p-conductivity type dopant; forming an interlayer insulation film on the surface of the second silicon oxide film; forming contact holes in the interlayer insulation film; implanting boron difluoride into the interlayer insulation film after formation of the contact holes; forming a metal wiring film on the inside of the contact holes and the surface of the interlayer insulation film; removing portions of the metal film; and depositing silicon nitride film by plasma enhanced chemical vapor deposition.
Claim 2
Independent Claim 284 words
A method of forming a SRAM memory cell comprising the steps of: forming a polysilicon film on a silicon oxide substrate by chemical vapor deposition; removing portions of the polysilicon film to form holes; implanting boron difluoride ions into the remaining portions of the polysilicon film to form a gate electrode and source and drain electrodes; forming a first silicon oxide insulation film on the gate electrode and source and drain electrodes by chemical vapor deposition; removing portions of the first silicon oxide film on the source and drain electrodes by photolithography and etching to form contact holes; forming an amorphous silicon film on the inside of the contact holes and the surface of the first silicon oxide insulation film; performing annealing treatment on said amorphous silicon film to convert said amorphous silicon film into a polysilicon film; removing portions of the polysilicon film with the remaining portions serving as an active region; oxidizing the active region at 850° C. to form a second silicon oxide film on the active region and simultaneously form a gate oxide film at the interface between the active region and the first silicon oxide film; forming source and drain regions adjacent opposing sides of the gate electrode by ion implantation of a p-conductivity type dopant; forming an interlayer insulation film on the surface of the second silicon oxide film; forming contact holes in the interlayer insulation film; implanting boron difluoride into the interlayer insulation film after formation of the contact holes; forming a metal wiring film on the inside of the contact holes and the surface of the interlayer insulation film; removing portions of the metal film; and depositing silicon nitride film by plasma enhanced chemical vapor deposition.

References Cited (Backward Citations)

US4797108A Cited
US5198379A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-03-12 1999-09-11 2000-03-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-03-12 2003-09-11 2004-03-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-03-12 2007-09-11 2008-03-12 $7700.00 Window Closed / Lapsed

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