US5474941A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for producing an active matrix substrate
Assignee: Sharp Corp
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Filing: 1993-11-18
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Granted: 1995-12-12
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Expires: 2013-11-18
Abstract
Abstract A method for producing an active matrix substrate using a thin film transistor having a gate electrode on an insulating substrate covered with a gate insulating layer, a semiconductor layer on the gate insulating layer, a channel protective layer on the semiconductor layer, a drain electrode having a portion overlying the gate electrode with the interposition of the gate insulating layer, the semiconductor layer and the channel protective layer, and a source electrode having a portion overlying the gate electrode with the interposition of the gate insulating layer, the method enhancing the transistor characteristics of the active matrix substrate with minimum leakage and the removal of an off-current generated from the presence of electrons and holes.
Inventors
- 👤 Yasuhiro Mitani
- 👤 Hirohisa Tanaka
- 👤 Hirosshi Morimoto
- 👤 Tomohiko Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 02:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0316; H10D30/6704; H10D30/6713; H10D30/6729; H10D30/673; H10D30/6731; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; H10D30/0321
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
166 words
A method for producing an active matrix substrate which uses a thin transistor layer having a semiconductor layer having a contact region and a channel region, a gate insulating layer, a gate electrode formed on a substrate in this sequence, a source electrode and a drain electrode each kept in contact with the contact region, the source electrode and the drain electrode partly overlapping with end portions of the semiconductor layer which end portions are wider than the gate insulating layer and the gate electrode, the gate insulating layer having declined sides wherein the sides thereof adjacent the gate electrode form a narrower top surface than a bottom surface thereof toward the substrate, and wherein ions are implanted into the semiconductor layer from the gate electrode such that a contact layer is formed in a portion of the semiconductor layer overlapping with at least part of the declining sides of the gate insulating layer and part of the semiconductor layer extending beyond the gate insulating layer.
Claim 2
Independent Claim
166 words
A method for producing an active matrix substrate which uses a thin transistor layer having a semiconductor layer having a contact region and a channel region, a gate insulating layer, a gate electrode formed on a substrate in this sequence, a source electrode and a drain electrode each kept in contact with the contact region, the source electrode and the drain electrode partly overlapping with end portions of the semiconductor layer which end portions are wider than the gate insulating layer and the gate electrode, the gate insulating layer having declined sides wherein the sides thereof adjacent the gate electrode form a narrower top surface than a bottom surface thereof toward the substrate, and wherein ions are implanted into the semiconductor layer from the gate electrode such that a contact layer is formed in a portion of the semiconductor layer overlapping with at least part of the declining sides of the gate insulating layer and part of the semiconductor layer extending beyond the gate insulating layer.
Claim 3
Dependent Claim
27 words
A method according to claim 1, wherein the source electrode and the drain electrode overlap at least part of the declining sides of the gate insulating layer.
Claim 4
Dependent Claim
27 words
A method according to claim 2, wherein end portions of the gate electrode coincide with end portions of the narrower top surface of the gate insulting layer.
Claim 5
Dependent Claim
34 words
A method according to claim 3, wherein one of the declining sides of the gate insulating layer is declined at 10° to 70° with respect to the bottom surface of the gate insulating layer.
Claim 6
Independent Claim
136 words
A method for producing an active matrix substrate comprising the steps of: forming a semiconductor layer on a transparent insulating substrate; forming a gate insulating layer on the semiconductor layer, the gate insulating layer having declining sides, wherein the sides thereof form a narrower top surface than a bottom surface thereof toward the transparent insulating substrate; forming a gate electrode on the narrower top surface of the gate insulating layer; forming a contact region in a portion of the semiconductor layer by an ion implanting method, the contact region overlapping at least part of the declining sides of the gate insulating layer and part of the semiconductor layer extending beyond the gate insulating layer, and wherein end portions of the gate electrode coincide with end portions of the narrower top surface of the gate insulating layer.
Claim 7
Independent Claim
136 words
A method for producing an active matrix substrate comprising the steps of: forming a semiconductor layer on a transparent insulating substrate; forming a gate insulating layer on the semiconductor layer, the gate insulating layer having declining sides, wherein the sides thereof form a narrower top surface than a bottom surface thereof toward the transparent insulating substrate; forming a gate electrode on the narrower top surface of the gate insulating layer; forming a contact region in a portion of the semiconductor layer by an ion implanting method, the contact region overlapping at least part of the declining sides of the gate insulating layer and part of the semiconductor layer extending beyond the gate insulating layer, and wherein end portions of the gate electrode coincide with end portions of the narrower top surface of the gate insulating layer.
Claim 8
Dependent Claim
36 words
A method according to claim 5, wherein the method further includes the step of: forming an electrode on the contact region, the electrode overlapping at least part of the declining sides of the gate insulating layer.
Claim 9
Dependent Claim
34 words
A method according to claim 5, wherein one of the declining sides of the gate insulating layer is declined at 10° to 70° with respect to the bottom surface of the gate insulating layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-11 | 1999-06-12 | 1999-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-11 | 2003-06-12 | 2003-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-11 | 2007-06-12 | 2007-12-12 | $7700.00 | Window Closed / Lapsed |