US5213990A
Expired / Lapsed
US
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Method for forming a stacked semiconductor structure
Assignee: Texas Instruments Inc
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Filing: 1992-04-01
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Granted: 1993-05-25
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Expires: 2012-04-01
Abstract
Abstract A method for connecting different conducting layers of a microelectronic device is disclosed. The method comprises: providing a first conducting layer (40); forming a first insulating layer (42) over said first conducting layer (40); forming a second conducting layer over said first insulating layer (42); patterning said second conducting layer to form a conducting element (44) over said first insulating layer (42) whereby the top surface of said first insulating layer (42) is protected from deleterious effects of further process steps; forming a second insulating layer (46) over said conducting element (44) and said first insulating layer (42) selectively removing said first insulating layer (42) and said second insulating layer (46), using an etch process which is selective over said insulating layers (42, 46) said conducting element (44) and said first conducting layer (40), to form a contact region (48) which straddles an edge of said conducting element (44) such that a portion of said conducting element (44) is exposed adjacent to an exposed portion of said conducting layer (40) with said first insulating layer (42) vertically interposed; and forming a third conducting layer (50) within said contact area (48). Other methods are also disclosed.
Inventors
- 👤 Mark S. Rodder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:30
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10B; H10B10/00; H10B10/12; H10B10/125; H10D30/027; H10D30/0275; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/109; Y10S438/00; Y10S438/906
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
230 words
A method of forming a stacked transistor structure comprising the steps of: a) forming first and second insulating regions defining a moat area in a semiconductor surface; b) forming a first gate insulator over said moat area; c) forming a gate over said first gate insulator; d) forming a second gate insulator which is a TFT gate insulator over said gate, such that said gate is a common gate for a first MOSFET transistor formed in said moat area and a second MOSFET transistor which is a first TFT; e) forming a TFT channel layer overlying said second gate insulator whereby the top surface of regions of said second gate insulator is protected from deleterious effects of further process steps; f) patterning said TFT channel layer to form a first channel region for said first TFT and a second channel region for a second TFT; g) forming a first insulating layer over said TFT channel regions and said TFT gate insulator; (h) selectively removing, using a selective etching process having an etching rate much greater for said first insulating layer and said TFT gate insulator than said TFT channel regions, said first insulating layer and said TFT gate insulator to form a contact region overlying an area of said first TFT channel region and an area of said common gate; and i) forming a conducting layer within said contact region.
Claim 2
Independent Claim
230 words
A method of forming a stacked transistor structure comprising the steps of: a) forming first and second insulating regions defining a moat area in a semiconductor surface; b) forming a first gate insulator over said moat area; c) forming a gate over said first gate insulator; d) forming a second gate insulator which is a TFT gate insulator over said gate, such that said gate is a common gate for a first MOSFET transistor formed in said moat area and a second MOSFET transistor which is a first TFT; e) forming a TFT channel layer overlying said second gate insulator whereby the top surface of regions of said second gate insulator is protected from deleterious effects of further process steps; f) patterning said TFT channel layer to form a first channel region for said first TFT and a second channel region for a second TFT; g) forming a first insulating layer over said TFT channel regions and said TFT gate insulator; (h) selectively removing, using a selective etching process having an etching rate much greater for said first insulating layer and said TFT gate insulator than said TFT channel regions, said first insulating layer and said TFT gate insulator to form a contact region overlying an area of said first TFT channel region and an area of said common gate; and i) forming a conducting layer within said contact region.
Claim 3
Dependent Claim
25 words
The method of claim 1 wherein said conducting layer is formed using selective growth techniques whereby said conducting layer is self-aligned within said contact region.
Claim 4
Dependent Claim
35 words
The method of claim 1 wherein said conducting layer is formed using selective epitaxial growth techniques comprising in-situ cleaning techniques whereby interfacial oxides are removed from said common gate and said second TFT channel region.
Claim 5
Independent Claim
245 words
A method of forming a transistor structure comprising the steps of: a) forming first and second insulating regions defining a moat area in a semiconductor surface; b) forming a gate insulator over said moat area; c) forming a first gate over said gate insulator; d) forming an interlevel insulator over the entirety of said moat area; e) patterning said interlevel insulator over said first gate to form a first contact hole; f) forming a second gate, which serves as a bottom gate for a first TFT, over said interlevel insulator and electrically connected to said first gate through said contact hole; g) forming a TFT gate insulator over said TFT bottom gate; h) forming a TFT channel layer over said TFT gate insulator whereby said TFT gate insulator is protected from deleterious effects of further process steps; i) patterning said TFT channel layer to form a first channel region for said first TFT and a second channel region for a second TFT; j) forming a first insulating layer over said TFT channel regions and said TFT gate insulator; k) selectively removing, using a selective etching process having an etching rate much greater for said first insulating layer and said TFT gate insulator than said TFT channel regions, said first insulating layer and said TFT gate insulator to form a contact region straddling an area of said second TFT channel region and said TFT bottom gate; and l) forming a conducting layer within said contact region.
Claim 6
Independent Claim
245 words
A method of forming a transistor structure comprising the steps of: a) forming first and second insulating regions defining a moat area in a semiconductor surface; b) forming a gate insulator over said moat area; c) forming a first gate over said gate insulator; d) forming an interlevel insulator over the entirety of said moat area; e) patterning said interlevel insulator over said first gate to form a first contact hole; f) forming a second gate, which serves as a bottom gate for a first TFT, over said interlevel insulator and electrically connected to said first gate through said contact hole; g) forming a TFT gate insulator over said TFT bottom gate; h) forming a TFT channel layer over said TFT gate insulator whereby said TFT gate insulator is protected from deleterious effects of further process steps; i) patterning said TFT channel layer to form a first channel region for said first TFT and a second channel region for a second TFT; j) forming a first insulating layer over said TFT channel regions and said TFT gate insulator; k) selectively removing, using a selective etching process having an etching rate much greater for said first insulating layer and said TFT gate insulator than said TFT channel regions, said first insulating layer and said TFT gate insulator to form a contact region straddling an area of said second TFT channel region and said TFT bottom gate; and l) forming a conducting layer within said contact region.
Claim 7
Dependent Claim
25 words
The method of claim 4 wherein said conducting layer is formed using selective growth techniques whereby said conducting layer is self-aligned within said contact region.
Claim 8
Dependent Claim
36 words
The method of claim 4 wherein said conducting layer is formed using selective epitaxial growth techniques comprising in-situ cleaning techniques whereby interfacial oxides are removed from said TFT bottom gate and said second TFT channel region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |