US5128738A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit
Assignee: Nokia Bell Labs
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Filing: 1991-05-16
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Granted: 1992-07-07
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Expires: 2011-05-16
Abstract
Abstract A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connetion between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.
Inventors
- 👤 Kuo-Hua Lee
- 👤 William J. Nagy
- 👤 Janmye Sung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 05:01
CPC Classifications
H; H10; H10B; H10B10/00; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/435; H10B10/15
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
93 words
A semiconductor integrated circuit comprising: a gate structure; a source or drain region proximate said gate; a first dielectric covering said gate; a first material layer covering said first dielectric; a second dielectric at least partially covering said first material layer; said first and second dielectrics having first and second openings respectively which together expose said source or drain region; a second material layer partially covering said second dielectric and contacting said source or drain region and said first material layer AND CHARACTERIZED IN THAT said second opening extends over said gate structure.
Claim 2
Dependent Claim
93 words
A semiconductor integrated circuit comprising: a gate structure; a source or drain region proximate said gate; a first dielectric covering said gate; a first material layer covering said first dielectric; a second dielectric at least partially covering said first material layer; said first and second dielectrics having first and second openings respectively which together expose said source or drain region; a second material layer partially covering said second dielectric and contacting said source or drain region and said first material layer AND CHARACTERIZED IN THAT said second opening extends over said gate structure.
Claim 3
Dependent Claim
11 words
The circuit of claim 1 wherein said first material is polysilicon.
Claim 4
Dependent Claim
11 words
The circuit of claim 1 wherein said second material is polysilicon.
Claim 5
Dependent Claim
18 words
The circuit of claim 1 wherein said first material at least partially covers said source or drain region.
References Cited (Backward Citations)
US4792841A
Cited
JPS59231851A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-07 | 1996-01-06 | 1996-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-07 | 2000-01-06 | 2000-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-07 | 2004-01-06 | 2004-07-07 | $7700.00 | Window Closed / Lapsed |