US5366909A
Expired / Lapsed
US
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Method for fabricating thin film transistor
Assignee: SK Hynix Inc
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Filing: 1994-02-23
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Granted: 1994-11-22
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Expires: 2014-02-23
Abstract
Abstract A method for fabricating a thin film transistor capable of increasing an ON/OFF current ratio and decreasing a consumption of electric power. The method includes the steps of sequentially depositing an insulating film and a first, high concentration p type semiconductor layer over a substrate, selectively removing a portion of the first semiconductor layer corresponding to a channel region, thereby forming a source region and a drain region, depositing a second, undoped semiconductor layer over the entire exposed surface of the resulting structure and implanting ions for controlling a threshold voltage in the second semiconductor layer, sequentially depositing a gate insulating film and a third semiconductor layer for a gate electrode over the entire exposed surface of the resulting structure and patterning the third semiconductor layer and the gate insulating film such that the third semiconductor layer and the gate insulating film are overlapped with the source region while being offset to the drain region, thereby forming the gate electrode, implanting p type impurity ions in a low concentration in an exposed portion of the second semiconductor layer using the gate electrode as a mask, and diffusing the p type impurity ions doped in both the source region and the drain region into the second semiconductor layer.
Inventors
- 👤 Seung R. Song
- 👤 Hong S. Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:32
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10B; H10B10/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/6717; Y; Y10; Y10S; Y10S148/00; Y10S148/15
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
198 words
A method for fabricating a thin film transistor, comprising the steps of: sequentially depositing an insulating film and a first, high concentration semiconductor layer of a first conductivity type over a substrate; selectively removing a portion of said first semiconductor layer corresponding to a channel region, thereby forming a source region and a drain region; depositing a second, undoped semiconductor layer over the entire exposed surface of the resulting structure and implanting ions for controlling a threshold voltage in said second semiconductor layer; sequentially depositing a gate insulating film and a third semiconductor layer for a gate electrode over the entire exposed surface of the resulting structure and patterning said third semiconductor layer and said gate insulating film such that the third semiconductor layer and the gate insulating film are overlapped with said source region while being offset to said drain region, thereby forming said gate electrode; implanting impurity ions of the first conductivity type in a low concentration in an exposed portion of the second semiconductor layer using the gate electrode as a mask; and diffusing said first conductivity type impurity ions doped in both the source region and the drain region into the second semiconductor layer.
Claim 2
Independent Claim
198 words
A method for fabricating a thin film transistor, comprising the steps of: sequentially depositing an insulating film and a first, high concentration semiconductor layer of a first conductivity type over a substrate; selectively removing a portion of said first semiconductor layer corresponding to a channel region, thereby forming a source region and a drain region; depositing a second, undoped semiconductor layer over the entire exposed surface of the resulting structure and implanting ions for controlling a threshold voltage in said second semiconductor layer; sequentially depositing a gate insulating film and a third semiconductor layer for a gate electrode over the entire exposed surface of the resulting structure and patterning said third semiconductor layer and said gate insulating film such that the third semiconductor layer and the gate insulating film are overlapped with said source region while being offset to said drain region, thereby forming said gate electrode; implanting impurity ions of the first conductivity type in a low concentration in an exposed portion of the second semiconductor layer using the gate electrode as a mask; and diffusing said first conductivity type impurity ions doped in both the source region and the drain region into the second semiconductor layer.
Claim 3
Dependent Claim
33 words
A method for fabricating a thin film transistor in accordance with claim 1, wherein said first semiconductor layer is comprised of an in-situ doped polysilicon layer or an in-situ doped amorphous silicon layer.
Claim 4
Dependent Claim
68 words
A method for fabricating a thin film transistor in accordance with claim 1, wherein said step of depositing said second semiconductor layer comprises the steps of depositing an amorphous silicon layer over the entire exposed surface of the resulting structure after the formation of said source region and said drain region, implanting silicon ions in said amorphous silicon layer, and annealing the resulting structure at a high temperature.
Claim 5
Independent Claim
224 words
A method for fabricating a thin film transistor, comprising the steps of: sequentially depositing a first insulating film and a first, high concentration semiconductor layer of a first conductivity type over a substrate; selectively removing a portion of said first semiconductor layer corresponding to a channel region, thereby forming a source region and a drain region; forming side walls comprised of a second insulating film on facing side surfaces of said source region and said drain region defining a channel region; depositing a second, undoped semiconductor layer over the entire exposed surface of the resulting structure and implanting ions for controlling a threshold voltage in said second semiconductor layer; sequentially depositing a gate insulating film and a third semiconductor layer for a gate electrode over the entire exposed surface of the resulting structure and patterning said third semiconductor layer and said gate insulating film such that the third semiconductor layer and the gate insulating film are overlapped with said source region while being offset to said drain region, thereby forming said gate electrode; implanting impurity ions of the first conductivity type in a low concentration in an exposed portion of the second semiconductor layer using the gate electrode as a mask; and diffusing said first conductivity type impurity ions doped in both the source region and the drain region into the second semiconductor layer.
Claim 6
Independent Claim
224 words
A method for fabricating a thin film transistor, comprising the steps of: sequentially depositing a first insulating film and a first, high concentration semiconductor layer of a first conductivity type over a substrate; selectively removing a portion of said first semiconductor layer corresponding to a channel region, thereby forming a source region and a drain region; forming side walls comprised of a second insulating film on facing side surfaces of said source region and said drain region defining a channel region; depositing a second, undoped semiconductor layer over the entire exposed surface of the resulting structure and implanting ions for controlling a threshold voltage in said second semiconductor layer; sequentially depositing a gate insulating film and a third semiconductor layer for a gate electrode over the entire exposed surface of the resulting structure and patterning said third semiconductor layer and said gate insulating film such that the third semiconductor layer and the gate insulating film are overlapped with said source region while being offset to said drain region, thereby forming said gate electrode; implanting impurity ions of the first conductivity type in a low concentration in an exposed portion of the second semiconductor layer using the gate electrode as a mask; and diffusing said first conductivity type impurity ions doped in both the source region and the drain region into the second semiconductor layer.
References Cited (Backward Citations)
US4294555A
Cited
JPS61105869A
Cited
US4943837A
Cited
JPH022523A
Cited
JPH02206132A
Cited
US5100810A
Cited
JPH04120738A
Cited
JPH04213430A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |