Method of forming trench transistor and isolation trench

Claim 1

A method of forming an IGFET and an isolation trench, comprising the steps of: simultaneously forming a transistor trench and an isolation trench in a substrate, wherein the transistor trench includes first and second opposing sidewalls and a first bottom surface, and the isolation trench includes third and fourth opposing sidewalls and a second bottom surface; forming first and second spacers adjacent to the first and second sidewalls, respectively; forming a gate insulator on the first bottom surface; forming a gate electrode on the gate insulator and the spacers; and forming a source and a drain in the substrate and adjacent to the first bottom surface.

Claim 2

A method of forming an IGFET and an isolation trench, comprising the steps of: simultaneously forming a transistor trench and an isolation trench in a substrate, wherein the transistor trench includes first and second opposing sidewalls and a first bottom surface, and the isolation trench includes third and fourth opposing sidewalls and a second bottom surface; forming first and second spacers adjacent to the first and second sidewalls, respectively; forming a gate insulator on the first bottom surface; forming a gate electrode on the gate insulator and the spacers; and forming a source and a drain in the substrate and adjacent to the first bottom surface.

Claim 12

A method of forming an IGFET and an isolation trench filled with an insulator for providing device isolation for the IGFET, comprising the steps of: simultaneously etching a transistor trench and an isolation trench in a semiconductor substrate, wherein the transistor trench includes first and second opposing sidewalls and a first bottom surface, the isolation trench includes third and fourth opposing sidewalls and a second bottom surface, and the first and second bottom surfaces have essentially identical depths beneath a top surface of the substrate; simultaneously forming first and second spacers adjacent to the first and second sidewalls, respectively, and third and fourth spacers adjacent to the third and fourth sidewalls, respectively; simultaneously forming a gate insulator on a central portion of the first bottom surface between the first and second spacers and an insulative region on a central portion of the second bottom surface between the third and fourth spacers; depositing a gate electrode material over the substrate, on the first, second, third and fourth spacers, on the gate insulator and insulative region, and into the trenches; polishing the gate electrode material such that a first portion of the gate electrode material in the transistor trench provides a gate electrode and a second portion of gate electrode material is in the isolation trench; and forming a source and a drain in the substrate, wherein the source is adjacent to the first bottom surface and the first sidewall and the top surface, and the drain is adjacent to the first bottom surface and the second sidewall and the top surface.

Claim 13

A method of forming an IGFET and an isolation trench filled with an insulator for providing device isolation for the IGFET, comprising the steps of: simultaneously etching a transistor trench and an isolation trench in a semiconductor substrate, wherein the transistor trench includes first and second opposing sidewalls and a first bottom surface, the isolation trench includes third and fourth opposing sidewalls and a second bottom surface, and the first and second bottom surfaces have essentially identical depths beneath a top surface of the substrate; simultaneously forming first and second spacers adjacent to the first and second sidewalls, respectively, and third and fourth spacers adjacent to the third and fourth sidewalls, respectively; simultaneously forming a gate insulator on a central portion of the first bottom surface between the first and second spacers and an insulative region on a central portion of the second bottom surface between the third and fourth spacers; depositing a gate electrode material over the substrate, on the first, second, third and fourth spacers, on the gate insulator and insulative region, and into the trenches; polishing the gate electrode material such that a first portion of the gate electrode material in the transistor trench provides a gate electrode and a second portion of gate electrode material is in the isolation trench; and forming a source and a drain in the substrate, wherein the source is adjacent to the first bottom surface and the first sidewall and the top surface, and the drain is adjacent to the first bottom surface and the second sidewall and the top surface.

Claim 23

A method of forming an IGFET adjacent to an isolation trench filled with oxide for providing device isolation for the IGFET, comprising the steps of: providing a semiconductor substrate with a planar top surface; forming a first masking layer over the substrate, wherein the first masking layer defines lateral boundaries for a transistor trench and an isolation trench; applying a first anisotropic etch using the first masking layer as an etch mask to simultaneously form the transistor trench and the isolation trench in the substrate, wherein the transistor trench includes first and second opposing vertical sidewalls and a first bottom surface, the isolation trench includes third and fourth opposing vertical sidewalls and a second bottom surface, and the first and second bottom surfaces have essentially identical depths beneath the top surface; stripping the first masking layer; depositing a first oxide layer over the substrate so as to fill the trenches; applying a second anisotropic etch to the first oxide layer to simultaneously form first and second oxide spacers adjacent to the first and second sidewalls, respectively, and third and fourth oxide spacers adjacent to the third and fourth sidewalls, respectively, such that a central portion of the first bottom surface between the first and second oxide spacers is exposed, and a central portion of the second bottom surface between the third and fourth oxide spacers is exposed; simultaneously growing a gate oxide on the central portion of the first bottom surface and an oxide region on the central portion of the second bottom surface; depositing a polysilicon layer over the substrate, on the first, second, third and fourth oxide spacers, and on the gate oxide and oxide region, so as to fill the trenches; polishing the polysilicon layer until the polysilicon layer does not overlap the top surface and the polysilicon layer forms a polysilicon gate electrode in the transistor trench and a polysilicon region in the isolation trench, wherein the polysilicon gate electrode is electrically isolated from the substrate and substantially all of the polysilicon gate electrode is within the transistor trench; forming a source and a drain in the substrate, wherein the source is adjacent to the first bottom surface and the first sidewall and the top surface, and the drain is adjacent to the first bottom surface and the second sidewall and the top surface; providing a second masking layer over the substrate, wherein the second masking layer covers the transistor trench and exposes the isolation trench; removing the polysilicon region from the isolation trench without removing the gate electrode from the transistor trench using the second masking layer as an etch mask; stripping the second masking layer; and depositing a second oxide layer over the substrate so as to fill the isolation trench with oxide.

Claim 24

A method of forming an IGFET adjacent to an isolation trench filled with oxide for providing device isolation for the IGFET, comprising the steps of: providing a semiconductor substrate with a planar top surface; forming a first masking layer over the substrate, wherein the first masking layer defines lateral boundaries for a transistor trench and an isolation trench; applying a first anisotropic etch using the first masking layer as an etch mask to simultaneously form the transistor trench and the isolation trench in the substrate, wherein the transistor trench includes first and second opposing vertical sidewalls and a first bottom surface, the isolation trench includes third and fourth opposing vertical sidewalls and a second bottom surface, and the first and second bottom surfaces have essentially identical depths beneath the top surface; stripping the first masking layer; depositing a first oxide layer over the substrate so as to fill the trenches; applying a second anisotropic etch to the first oxide layer to simultaneously form first and second oxide spacers adjacent to the first and second sidewalls, respectively, and third and fourth oxide spacers adjacent to the third and fourth sidewalls, respectively, such that a central portion of the first bottom surface between the first and second oxide spacers is exposed, and a central portion of the second bottom surface between the third and fourth oxide spacers is exposed; simultaneously growing a gate oxide on the central portion of the first bottom surface and an oxide region on the central portion of the second bottom surface; depositing a polysilicon layer over the substrate, on the first, second, third and fourth oxide spacers, and on the gate oxide and oxide region, so as to fill the trenches; polishing the polysilicon layer until the polysilicon layer does not overlap the top surface and the polysilicon layer forms a polysilicon gate electrode in the transistor trench and a polysilicon region in the isolation trench, wherein the polysilicon gate electrode is electrically isolated from the substrate and substantially all of the polysilicon gate electrode is within the transistor trench; forming a source and a drain in the substrate, wherein the source is adjacent to the first bottom surface and the first sidewall and the top surface, and the drain is adjacent to the first bottom surface and the second sidewall and the top surface; providing a second masking layer over the substrate, wherein the second masking layer covers the transistor trench and exposes the isolation trench; removing the polysilicon region from the isolation trench without removing the gate electrode from the transistor trench using the second masking layer as an etch mask; stripping the second masking layer; and depositing a second oxide layer over the substrate so as to fill the isolation trench with oxide.