Patent US5757703A successfully refreshed from Google Patents.
US5757703A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Distributed write data drivers for burst access memories
Assignee: Round Rock Research LLC
•
Filing: 1997-01-21
•
Granted: 1998-05-26
•
Expires: 2017-01-21
Abstract
Abstract An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.
Inventors
- 👤 Todd A. Merritt
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:35
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/109; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/1024; G11C7/1039; G11C7/1045; G11C7/1096; G11C7/22; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
220 words
A memory device comprising: a memory element array region; a control circuit region; a plurality of data line pairs dispersed throughout the memory element array region, each of the data line pairs comprising a true data line and a compliment data line; a plurality of equilibration devices, each of the equilibration devices coupled to the true data line and the compliment data line of one of the plurality of data line pairs, and each of the equilibration devices responsive to an equilibrate signal from the control circuit region to couple the true data line to the compliment data; a plurality of data sense amplifiers, each proximately located at least one of the data line pairs; and a distributed plurality of write data drivers each comprising an equilibrate inactive input responsive to the equilibrate signal, a write active input responsive to a write enable signal from the control circuit region, a true write data output coupled to the true data line of one of the data line pairs and a compliment write data output coupled to the compliment data line of one of the data line pairs for driving data on the data line pairs in response to the equilibrate and write enable signals, each of the write data drivers proximately located to at least one of the data sense amplifiers.
Claim 2
Dependent Claim
220 words
A memory device comprising: a memory element array region; a control circuit region; a plurality of data line pairs dispersed throughout the memory element array region, each of the data line pairs comprising a true data line and a compliment data line; a plurality of equilibration devices, each of the equilibration devices coupled to the true data line and the compliment data line of one of the plurality of data line pairs, and each of the equilibration devices responsive to an equilibrate signal from the control circuit region to couple the true data line to the compliment data; a plurality of data sense amplifiers, each proximately located at least one of the data line pairs; and a distributed plurality of write data drivers each comprising an equilibrate inactive input responsive to the equilibrate signal, a write active input responsive to a write enable signal from the control circuit region, a true write data output coupled to the true data line of one of the data line pairs and a compliment write data output coupled to the compliment data line of one of the data line pairs for driving data on the data line pairs in response to the equilibrate and write enable signals, each of the write data drivers proximately located to at least one of the data sense amplifiers.
Claim 3
Dependent Claim
42 words
The memory device of claim 1, further comprising: a mode select circuit adapted to select between a mode of operation from at least EDO and Burst EDO modes, wherein the distributed plurality of write data drivers are each responsive to the mode.
Claim 4
Independent Claim
140 words
A method of writing data into a memory device comprising steps of: providing an address for the memory device; asserting an equilibrate signal which is coupled to an equilibration device in order to equilibrate internal data lines of the memory device in response to the step of providing an address; coupling the equilibrate signal to a plurality of data driver enable circuits; coupling a write enable signal to the plurality of data driver enable circuits; deasserting the equilibrate signal after the internal data lines are equilibrated; gating the write enable signal through at least one of the data driver enable circuits in response to the step of deasserting the equilibrate signal; driving data onto the internal data lines in response to the step of gating; and storing data in a memory cell in response to the step of driving data.
Claim 5
Independent Claim
140 words
A method of writing data into a memory device comprising steps of: providing an address for the memory device; asserting an equilibrate signal which is coupled to an equilibration device in order to equilibrate internal data lines of the memory device in response to the step of providing an address; coupling the equilibrate signal to a plurality of data driver enable circuits; coupling a write enable signal to the plurality of data driver enable circuits; deasserting the equilibrate signal after the internal data lines are equilibrated; gating the write enable signal through at least one of the data driver enable circuits in response to the step of deasserting the equilibrate signal; driving data onto the internal data lines in response to the step of gating; and storing data in a memory cell in response to the step of driving data.
Claim 6
Dependent Claim
18 words
The method of claim 3 wherein the step of providing an address is completed using an external microprocessor.
Claim 7
Dependent Claim
14 words
The method of claim 4 wherein the data is provided from the external microprocessor.
References Cited (Backward Citations)
US4344156A
Cited
US4484308A
Cited
US4562555A
Cited
US4575825A
Cited
US4603403A
Cited
US4567579A
Cited
US4707811A
Cited
US4875192A
Cited
US4618947B1
Cited
US4618947A
Cited
US4685089A
Cited
US4649522A
Cited
US4788667A
Cited
US5267200A
Cited
US5268865A
Cited
US5357469A
Cited
US5392239A
Cited
US5430680A
Cited
US5452259A
Cited
US5526320A
Cited
US5598376A
Cited
US5610864A
Cited
US5612918A
Cited
US5619466A
Cited
US5657292A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-25 | 2001-11-24 | 2002-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-25 | 2005-11-24 | 2006-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-25 | 2009-11-24 | 2010-05-26 | $7700.00 | Window Closed / Lapsed |