US5610864A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Burst EDO memory device with maximized write cycle timing
Assignee: Round Rock Research LLC
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Filing: 1995-02-10
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Granted: 1997-03-11
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Expires: 2015-02-10
Abstract
Abstract An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access, reset the burst length counter and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies.
Inventors
- 👤 Troy A. Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:25
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/109; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0638; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/1015; G11C7/1018; G11C7/1021; G11C7/1024; G11C7/1039; G11C7/1045; G11C7/1096; G11C7/22; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
65 words
A memory device adapted to perform a write operation to store data in the memory device, the memory device comprising: a write operation control circuit adapted to switch control of a write operation between a write command signal and an access cycle signal during a write operation, wherein the write command signal initiates the write operation, and the access cycle signal terminates the write operation.
Claim 2
Dependent Claim
65 words
A memory device adapted to perform a write operation to store data in the memory device, the memory device comprising: a write operation control circuit adapted to switch control of a write operation between a write command signal and an access cycle signal during a write operation, wherein the write command signal initiates the write operation, and the access cycle signal terminates the write operation.
Claim 3
Dependent Claim
37 words
The memory device of claim 1, further comprising an array of memory elements, wherein the access cycle signal is operative to latch an address corresponding to a column of the array and to initiate an access cycle.
Claim 4
Dependent Claim
26 words
The memory device of claim 1, wherein said write operation control circuit comprises a multiplexer, said multiplexer producing a multiplexer output to control the write operation.
Claim 5
Dependent Claim
33 words
The memory device of claim 3, wherein said write operation control circuit further comprises a latch adapted to drive a latched select signal to said multiplexer to select control of the write operation.
Claim 6
Dependent Claim
32 words
The memory device of claim 1, further comprising a write command latch responsive to the access cycle signal and an externally generated write cycle control signal to create the write command signal.
Claim 7
Dependent Claim
23 words
The memory device of claim 5, further comprising a circuit to clear said write command latch at the beginning of an access cycle.
Claim 8
Dependent Claim
15 words
The memory device of claim 6, wherein said circuit to clear comprises a pulse generator.
Claim 9
Dependent Claim
93 words
A memory access cycle control circuit for a memory suitable to perform a write operation to store data in the memory device, the access cycle control circuit comprising: circuitry to terminate a first write operation in response to initiation of an access cycle by a transition of an access cycle signal; circuitry to initiate a second write operation in response to the transition of the access cycle signal after termination of the first write operation; and a latch to maintain the second write operation until a subsequent transition of the access cycle signal.
Claim 10
Dependent Claim
93 words
A memory access cycle control circuit for a memory suitable to perform a write operation to store data in the memory device, the access cycle control circuit comprising: circuitry to terminate a first write operation in response to initiation of an access cycle by a transition of an access cycle signal; circuitry to initiate a second write operation in response to the transition of the access cycle signal after termination of the first write operation; and a latch to maintain the second write operation until a subsequent transition of the access cycle signal.
Claim 11
Dependent Claim
68 words
A write cycle control circuit for a memory device, comprising: a write cycle command latch to store a latched write cycle command in response to an access cycle signal, the access cycle signal initiating a memory access cycle; and a pulse generator to clear said write cycle command latch in response to the access cycle signal prior to said write cycle command latch storing the write cycle command.
Claim 12
Dependent Claim
68 words
A write cycle control circuit for a memory device, comprising: a write cycle command latch to store a latched write cycle command in response to an access cycle signal, the access cycle signal initiating a memory access cycle; and a pulse generator to clear said write cycle command latch in response to the access cycle signal prior to said write cycle command latch storing the write cycle command.
Claim 13
Dependent Claim
45 words
The write cycle control circuit of claim 9, further comprising: a multiplexer, adapted to produce a write cycle control output signal, to select between the latched write cycle command and the access cycle signal to determine a state of the write cycle control output signal.
Claim 14
Dependent Claim
60 words
The write cycle control circuit of claim 9, further comprising: an access cycle pulse generator to generate an access cycle pulse signal in response to each edge of the access cycle signal, the access cycle pulse signal having a first and a second state within each access cycle which define a first and a second portion of each access cycle.
Claim 15
Dependent Claim
46 words
The write cycle control circuit of claim 11, further comprising: a multiplexer, adapted to produce a write cycle control output signal, to select between the latched write cycle command and the access cycle pulse signal to determine a state of the write cycle control output signal.
Claim 16
Independent Claim
55 words
A method of writing data in a memory device, comprising the following sequence of steps: intiating a write access cycle of the memory device with an access cycle signal; clearing a write command latch within the memory device; and latching a write command signal in the write command latch to control the write access cycle.
Claim 17
Independent Claim
55 words
A method of writing data in a memory device, comprising the following sequence of steps: intiating a write access cycle of the memory device with an access cycle signal; clearing a write command latch within the memory device; and latching a write command signal in the write command latch to control the write access cycle.
Claim 18
Dependent Claim
49 words
The method of claim 13, furhter comprising steps of: storing data in response to said step of latching the write command signal; initiating a further access cycle of the memory device; and terminating said step of storing data in response to said step of initiating the further access cycle.
Claim 19
Dependent Claim
27 words
The method of claim 14, wherein said step of storing data occurs throughout a period of time nearly equal to a duration of the write access cycle.
Claim 20
Dependent Claim
21 words
The method of claim 14, further comprising a step of: clearing the write command latch subsequent to said step of terminating.
Claim 21
Dependent Claim
47 words
The method of claim 13, further comprising steps of: storing data in response to said step of latching the write command signal; initiating a read cycle of the memory device; and terminating said step of storing data in response to said step of initiating the read cycle.
Claim 22
Dependent Claim
18 words
The method of claim 17, further comprising: clearing the write command latch subsequent to said step of terminating.
Claim 23
Dependent Claim
45 words
The method of claim 13, further comprising: storing data in response to said step of latching the write command signal; terminating a burst access of the memory device; and terminating said step of storing data in response to said step of terminating the burst access.
Claim 24
Dependent Claim
22 words
The method of claim 19, further comprising: clearing the write command latch subsequent to said step of terminating said step of storing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |