Redundancy architecture

Claim 2

A redundant decoder for selecting a redundant memory cell responsive to an address signal presented thereto, said redundant decoder comprising: one or more redundant select circuits, each comprising: an enable circuit, comprising a first permanently programmable selection element, having an output indicating whether or not the redundant select circuit is enabled responsive to the state of said first permanently programmable selection element; a plurality of pass elements connected in parallel, wherein each one of said pass elements has a conduction path, and has a control terminal coupled to the output of said enable circuit so that said pass elements are conductive responsive to the enablecircuit indicating that the redundant select circuit is enabled; a plurality of permanently programmable selection elements, wherein each one of said plurality of permanently programmable selection elements connected in series with the conduction path of one pass element between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output; wherein said input of each one of said plurality pass elements is coupled to one address line corresponding to the column address signal; and wherein a path of said input of said redundant select circuit consists of only one of said plurality of pass elements connected in series with one of said plurality of permanently programmable selection elements.

Claim 3

The redundant decoder of claim 1, wherein each one of said plurality of permanently programmable selection elements comprises a fuse, and wherein each fuse except one in said plurality of fuses is blown.

Claim 4

The redundant decoder of claim 1, wherein the number of said redundant select circuit in said redundant decoder is equal to the number of redundant columns associated with a block of memory.

Claim 5

The redundant decoder of claim 1, wherein the number of said redundant select circuits in said redundant decoder is equal to the number of redundant columns associated with two adjacent blocks of memory.

Claim 6

The redundant decoder of claim 1, wherein said redundant select circuit further comprises a test control circuit for placing each redundant memory cell connected into stress test mode responsive to a test control signal.

Claim 7

The redundant decoder of claim 1, wherein said redundant select circuit further comprises an isolation circuit for isolating said redundant memory cells responsive to a sense isolation signal.

Claim 8

The redundant decoder of claim 1, wherein each said pass element in said redundant select circuit comprises a pass gate of complementary transistors having their conduction paths connected in parallel.

Claim 9

A redundant decoder for selecting a redundant memory cell responsive to an address signal presented thereto, said redundant decoder comprising: one or more redundant select circuits, each comprising: an enable circuit, comprising a first fuse, having an output indicating whether or not the redundant select circuit is enabled responsive to the state of said first fuse; a plurality of pass gates connected in parallel, wherein each one of said pass gates has a conduction path, and has a control terminal coupled to the output of said enable circuit so that said pass gates are conductive responsive to the enable circuit indicating that the redundant select circuit is enabled, and a plurality of fuses, wherein each one of said plurality of fuses are each connected singly in series with the conduction path of one pass gate between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output.

Claim 10

A redundant decoder for selecting a redundant memory cell responsive to an address signal presented thereto, said redundant decoder comprising: one or more redundant select circuits, each comprising: an enable circuit, comprising a first fuse, having an output indicating whether or not the redundant select circuit is enabled responsive to the state of said first fuse; a plurality of pass gates connected in parallel, wherein each one of said pass gates has a conduction path, and has a control terminal coupled to the output of said enable circuit so that said pass gates are conductive responsive to the enable circuit indicating that the redundant select circuit is enabled, and a plurality of fuses, wherein each one of said plurality of fuses are each connected singly in series with the conduction path of one pass gate between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output.

Claim 11

The redundant decoder of claim 8, wherein each fuse except one in said plurality of fuses is blown.

Claim 12

The redundant decoder of claim 8, wherein said input of each one of said plurality of pass gates is coupled to one address line corresponding to the column address signal.

Claim 13

The redundant decoder of claim 10, wherein the number of said redundant select circuit in said redundant decoder is equal to the number of redundant columns associated with a block of memory.

Claim 14

The redundant decoder of claim 10, wherein the number of said redundant select circuits in said redundant decoder is equal to the number of redundant columns associated with two adjacent blocks of memory.

Claim 15

The redundant decoder of claim 8, wherein said redundant select circuit further comprises a test control circuit for placing each redundant memory cell connected into stress test mode responsive to a test control signal.

Claim 16

The redundant decoder of claim 8, wherein said redundant select circuit further comprises an isolation circuit for isolating said redundant memory cells responsive to a sense isolation signal.

Claim 17

The redundant decoder of claim 8, wherein each said pass gate in said redundant select circuit comprises complementary transistors having their conduction paths connected in parallel.

Claim 18

A memory comprising: a plurality of primary memory cells arranged in rows and columns; an accessing circuit for accessing a primary memory cell; a plurality of redundant memory cells; a redundant decoder for selecting a redundant memory cell responsive to an address signal presented thereto, said redundant decoder comprising at least one redundant select circuit, wherein each said redundant select circuit comprises: an enable circuit, comprising a first fuse, having an output indicating whether or not the redundant select circuit is enabled responsive to the state of said first fuse; a plurality of pass elements connected in parallel, wherein each one of said pass elements has a conduction path, and has a control terminal coupled to the output of said enable circuit so that said pass elements are conductive responsive to the enable circuit indicating that the redundant select circuit is enabled; and a plurality of fuses, wherein each one of said plurality of fuses are each connected singly in series with the conduction path of one pass element between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output.

Claim 19

A memory comprising: a plurality of primary memory cells arranged in rows and columns; an accessing circuit for accessing a primary memory cell; a plurality of redundant memory cells; a redundant decoder for selecting a redundant memory cell responsive to an address signal presented thereto, said redundant decoder comprising at least one redundant select circuit, wherein each said redundant select circuit comprises: an enable circuit, comprising a first fuse, having an output indicating whether or not the redundant select circuit is enabled responsive to the state of said first fuse; a plurality of pass elements connected in parallel, wherein each one of said pass elements has a conduction path, and has a control terminal coupled to the output of said enable circuit so that said pass elements are conductive responsive to the enable circuit indicating that the redundant select circuit is enabled; and a plurality of fuses, wherein each one of said plurality of fuses are each connected singly in series with the conduction path of one pass element between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output.

Claim 20

The memory of claim 16, wherein each fuse except one in said plurality of fuses is blown.

Claim 21

The memory of claim 16, wherein accessing circuit comprises an input/output multiplexer circuit.

Claim 22

The memory of claim 16, wherein said row and columns of said primary memory cells grouped into at least one block, with each said block divided into a plurality of input/output groups.

Claim 23

The memory of claim 19, wherein each one of said plurality of input/output groups has a plurality of columns.

Claim 24

The memory of claim 16, wherein said input of each one of said plurality of pass elements is coupled to one address line corresponding to the column address signal.

Claim 25

The memory of claim 21, further comprising a plurality of redundant input/output select circuits, with one redundant input/output select circuit within each input/output group, and with each redundant input/output select circuit coupled to each redundant column associated with the block containing said input/output group.

Claim 26

The memory of claim 21, wherein the number of said redundant select circuits in said redundant decoder is equal to the number of redundant columns associated with one said block.

Claim 27

The memory of claim 21, wherein the number of said redundant select circuits in said redundant decoder is equal to the number of redundant columns associated with two adjacent blocks of memory.

Claim 28

The memory of claim 16, wherein said redundant select circuit further comprises a test control circuit for placing each redundant memory cell connected into stress test mode responsive to a test control signal.

Claim 29

The redundant decoder of claim 16, wherein said redundant select circuit further comprises an isolation circuit for isolating said redundant memory cells responsive to a sense isolation signal.

Claim 30

The memory of claim 16, wherein each said pass element comprises a pass gate with complementary transistors having their conduction paths connected in parallel.

Claim 31

The memory of claim 16, wherein said plurality of said primary memory cell and said plurality of said redundant memory cells comprise a synchronous random access memory.

Claim 32

A redundancy structure of an integrated circuit memory device comprising: a plurality of primary memory cells arranged in rows and columns; an accessing circuit for accessing a primary memory cell; a plurality of redundant memory cells; a redundant decoder comprising at least one redundant select circuit for accessing a redundant memory cell responsive to an address signal presented thereto, comprising: a first fuse for enabling said redundant select circuit; a half latch comprising of a first transistor and an inverter for latching the logic state an the output of said first fuse when said redundant select circuit is enabled; a second transistor having its conduction path connected between said first fuse and ground and controlled by a power-on-reset signal for placing said half latch in the proper logic state upon power up; a logic element having a first input coupled to said inverter, a second input coupled to a test control signal, and an output; a third transistor having a control terminal coupled to said output of said logic element, for ensuring said redundant column is not selected responsive to said test control signal and said redundant select circuit not being enabled; a plurality of pass gates connected in parallel comprising complementary transistors having their conduction paths connected in parallel, wherein each one of said pass gates has a conduction path, and has a control terminal coupled to the output of said inverter and a control terminal coupled to said output of said logic element so that said pass gates are conductive responsive to the enable circuit indicating that the redundant select circuit is enabled; a plurality of fuses, wherein each one of said plurality of fuses connected in series with the conduction path of one pass gate between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output; and an NAND gate coupled to said third transistor and said plurality of fuses for isolating said redundant memory cells responsive to a sense isolation signal.

Claim 33

A redundancy structure of an integrated circuit memory device comprising: a plurality of primary memory cells arranged in rows and columns; an accessing circuit for accessing a primary memory cell; a plurality of redundant memory cells; a redundant decoder comprising at least one redundant select circuit for accessing a redundant memory cell responsive to an address signal presented thereto, comprising: a first fuse for enabling said redundant select circuit; a half latch comprising of a first transistor and an inverter for latching the logic state an the output of said first fuse when said redundant select circuit is enabled; a second transistor having its conduction path connected between said first fuse and ground and controlled by a power-on-reset signal for placing said half latch in the proper logic state upon power up; a logic element having a first input coupled to said inverter, a second input coupled to a test control signal, and an output; a third transistor having a control terminal coupled to said output of said logic element, for ensuring said redundant column is not selected responsive to said test control signal and said redundant select circuit not being enabled; a plurality of pass gates connected in parallel comprising complementary transistors having their conduction paths connected in parallel, wherein each one of said pass gates has a conduction path, and has a control terminal coupled to the output of said inverter and a control terminal coupled to said output of said logic element so that said pass gates are conductive responsive to the enable circuit indicating that the redundant select circuit is enabled; a plurality of fuses, wherein each one of said plurality of fuses connected in series with the conduction path of one pass gate between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output; and an NAND gate coupled to said third transistor and said plurality of fuses for isolating said redundant memory cells responsive to a sense isolation signal.

Claim 34

The memory of claim 29, wherein each fuse except one in said plurality of fuses is blown.

Claim 35

The redundancy structure of claim 29, wherein said input each one of said plurality of pass gates is coupled to one address line corresponding to the column address signal.

Claim 36

The redundancy structure of claim 31, wherein the number of said redundant select circuit in said redundant decoder is equal to the number of redundant columns associated with a block of memory.

Claim 37

The redundancy structure of claim 31, wherein the number of said redundant select circuit in said redundant decoder is equal to the number of redundant columns associated with two adjacent blocks of memory.

Claim 38

The redundancy structure of claim 29, wherein said logic element is a NOR gate.

Claim 39

A memory comprising: a plurality of primary memory cells arranged in rows and columns; an accessing circuit for accessing a primary memory cell; a plurality of redundant memory cells; a redundant decoder for selecting a redundant memory cell responsive to an address signal presented thereto, said redundant decoder comprising at least one redundant select circuit, wherein each said redundant select circuit comprises: an enable circuit, comprising a first fuse, having an output indicating whether or not the redundant select circuit is enabled responsive to the state of said first fuse; a plurality of pass gates connected in parallel, wherein each one of said pass gates has a conduction path, and has a control terminal coupled to the output of said enable circuit so that said pass gates are conductive responsive to the enable circuit indicating that the redundant select circuit is enabled, and a plurality of fuses, wherein each one of said plurality of fuses connected in series with the conduction path of one pass gate between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output; and one or more redundant input/output select circuit, with one redundant input/output select circuit associated with one of a plurality of input/output groups, wherein each redundant input/output select circuit comprises: one or more redundant input/output circuits, each comprising: a first permanently programmable selection element for disconnecting said redundant input/output circuit from a read bus true; and a second permanently programmable selection element for disconnecting said redundant input/output circuit from a read bus complement; and at least one equilibrate/precharge circuit coupled to said redundant input/output circuit, for precharging said redundant input/output circuit.

Claim 40

A memory comprising: a plurality of primary memory cells arranged in rows and columns; an accessing circuit for accessing a primary memory cell; a plurality of redundant memory cells; a redundant decoder for selecting a redundant memory cell responsive to an address signal presented thereto, said redundant decoder comprising at least one redundant select circuit, wherein each said redundant select circuit comprises: an enable circuit, comprising a first fuse, having an output indicating whether or not the redundant select circuit is enabled responsive to the state of said first fuse; a plurality of pass gates connected in parallel, wherein each one of said pass gates has a conduction path, and has a control terminal coupled to the output of said enable circuit so that said pass gates are conductive responsive to the enable circuit indicating that the redundant select circuit is enabled, and a plurality of fuses, wherein each one of said plurality of fuses connected in series with the conduction path of one pass gate between an input and an output of the redundant select circuit, for disconnecting, when opened, said input from said output; and one or more redundant input/output select circuit, with one redundant input/output select circuit associated with one of a plurality of input/output groups, wherein each redundant input/output select circuit comprises: one or more redundant input/output circuits, each comprising: a first permanently programmable selection element for disconnecting said redundant input/output circuit from a read bus true; and a second permanently programmable selection element for disconnecting said redundant input/output circuit from a read bus complement; and at least one equilibrate/precharge circuit coupled to said redundant input/output circuit, for precharging said redundant input/output circuit.

Claim 41

The memory of claim 35, wherein a path of said input of said redundant select circuit consists of only one of said plurality of pass gates connected in series with one of said plurality of fuses.

Claim 42

The memory of claim 35, wherein each fuse except one in said plurality of fuses is blown.

Claim 43

The memory of claim 35, wherein accessing circuit comprises an input/output multiplexer circuit.

Claim 44

The memory of claim 35, wherein said redundant select circuit further comprises a test control circuit for placing each redundant memory cell connected into stress test mode responsive to a test control signal.

Claim 45

The redundant decoder of claim 35, wherein said redundant select circuit further comprises an isolation circuit for isolating said redundant memory cells responsive to a sense isolation signal.

Claim 46

The memory of claim 35, wherein each said pass gate comprises complementary transistors having their conduction paths connected in parallel.

Claim 47

The memory of claim 35, wherein each one of said plurality of input/output groups has a plurality of adjacent columns.

Claim 48

The memory of claim 35, wherein said input of each one of said plurality of pass gates is coupled to an address line corresponding to the column address signal.

Claim 49

The memory of claim 43, wherein the number of said redundant select circuits in said redundant decoder is equal to the number of redundant columns associated with one said block.

Claim 50

The memory of claim 43, wherein the number of said redundant select circuits in said redundant decoder is equal to the number of redundant columns associated with two adjacent blocks of memory.

Claim 51

The memory of claim 35, wherein the number of said redundant input/output circuits in each one of said redundant input/output select circuit is equal to the number of redundant columns associated with a block of memory, with each redundant input/output circuit coupled to one redundant column.

Claim 52

The memory of claim 46, wherein said first and second permanently programmable selection elements disconnect said redundant input/output circuits from said read bus true and said read bus complement in each redundant input/output circuit coupled to an enabled redundant column in a redundant input/output select circuit not associated with an input/output group having a memory cell having a defect.

Claim 53

The memory of claim 35, wherein said first and second permanently programmable selection elements comprise a fuse.

Claim 54

The memory of claim 35, wherein said plurality of said primary memory cell and said plurality of said redundant memory cells comprise a synchronous random access memory.

Claim 55

The memory of claim 35, wherein said redundant input/output circuit further comprises: a first transistor having a conduction path coupled between said first permanently programmable selection element and a first bitline fuse coupled to a redundant bitline-true; and a second transistor having a conduction path coupled between said second permanently programmable selection element and a second fuse coupled to a redundant bitline-complement; wherein both said first and second transistors are controlled by an input of said redundant input/output circuit.

Claim 56

The memory of claim 35, wherein said redundant input/output circuit further comprises: a third transistor having a conduction path coupled between write bus true and redundant bitline-true; and a fourth transistor having a conduction path coupled between write bus complement and redundant bitline-complement; wherein both said third and said fourth transistors are controlled by an inverted input of said redundant input/output circuit.

Claim 59

The method of claim 52, wherein said input of each one of said plurality of pass elements is coupled to one address line corresponding to a column address signal.

Claim 60

The method of claim 52, further comprising the steps of: opening each first bitline fuse except one according to said determined column address value, wherein each first bitline fuse is coupled between a redundant bitline-true and a redundant input/output circuit in one of a plurality of redundant input/output select circuits; and, opening each second bitline fuse except one according to said determined column address value, wherein each second bitline fuse is coupled between a redundant bitline-complement and a redundant input/output circuit in one of said plurality of redundant input/output select circuits; wherein each one of said plurality of said redundant input/output circuits is coupled to said redundant decoder.

Claim 61

The method of claim 54, further comprising the steps of: opening each first permanently programmable selection element except one according to said determined address value, wherein each first permanently programmable selection element is coupled between a read bus true and a redundant input/output circuit in one of said plurality of redundant input/output select circuits; and opening each second permanently programmable selection element except one according to said determined address value, wherein each second permanently programmable selection element is coupled between a read bus complement and a redundant input/output circuit in one of said plurality of redundant input/output select circuits.

Claim 62

The method of claim 54, further comprising the steps of: opening a first fuse coupled between an input/output multiplexer circuit and a primary bitline-true according to said determined column address value; and opening a second fuse coupled between said input/output multiplexer circuit and a primary bitline-complement according to said determined column address value; wherein said input/output multiplexer circuit is associated with a redundant input/output select circuit having its fuse not opened.